Displaying 8 results from an estimated 8 matches for "hdls".
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2013 Aug 30
0
[LLVMdev] Reflexions about a new HDL language
If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools). Starting from comparisons to VHDL and Verilog is like designing a new high-level programming language today that is designed to be a better high-level programming language that is
2013 Aug 30
4
[LLVMdev] Reflexions about a new HDL language
Hi,
For the synthesis backend which translate to VHDL or Verilog, I don't
know if I will use LLVM. It will depend on how easy it is to play with
concurrent statements with LLVM. For the simulation I will use LLVM
because I can anyways artificially make the compiled code sequencial. It
would allow me to benefit from all the nice things from LLVM like
existing optimisations. I have never
2011 Oct 07
0
[LLVMdev] Vlang - TR : LLVM and VHDL simulation
...rformances and ease of developpement.
>This project has still to be accepted, so I am not 100% sure that I will do this project. I also found a tutorial (http://llvm.org/docs/tutorial/) that can help me to familiarize with LLVM before I will do this project (if I will).
If you are interested in HDLs perhaps you would be interested in Vlang?
I am currently working on Verilog fronted and I am looking for somebody with VHDL interest to join the Vlang project.
>Greetings
>Jonas
Cheers,
Pawel
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2011 Oct 10
0
[LLVMdev] Vlang - TR : LLVM and VHDL simulation
Hi Pavel,
> If you are interested in HDLs perhaps you would be interested in Vlang?
> I am currently working on Verilog fronted and I am looking for somebody with
> VHDL interest to join the Vlang project.
I have never heard about the Vlang project but it seems to be an interesting project. I think I
could be interested to join this...
2012 Oct 10
1
[LLVMdev] Inconsistency in the LLVM docs
Yes I know, I'm having problems with these tests because they violate the documentation. :)
Micah
From: Nadav Rotem [mailto:nrotem at apple.com]
Sent: Wednesday, October 10, 2012 11:52 AM
To: Villmow, Micah
Cc: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] Inconsistency in the LLVM docs
Hi Micah,
We need to fix the documentation here. We want to be able to convert vectors of integers to
2009 Feb 26
4
[LLVMdev] Shrink Wrapping - RFC and initial implementation
Hello LLVMdev,
I have been working with LLVM for just over a year now, mainly in the area
of compilation for HDLs like SystemVerilog and SystemC.
Most of this work dealt with translation to LLVM IR, representing concurrent
languages with LLVM and using LLVM analyses and transforms
for compiling onto proprietary simulation acceleration hardware. All of this
work used the C back end exclusively, since I wanted a...
2009 Mar 01
0
[LLVMdev] Shrink Wrapping - RFC and initial implementation
On Feb 26, 2009, at 2:02 PM, John Mosby wrote:
> Hello LLVMdev,
>
> I have been working with LLVM for just over a year now, mainly in
> the area of compilation for HDLs like SystemVerilog and SystemC.
> Most of this work dealt with translation to LLVM IR, representing
> concurrent languages with LLVM and using LLVM analyses and transforms
> for compiling onto proprietary simulation acceleration hardware. All
> of this work used the C back end exclu...
2016 Oct 14
3
Parallel IR [PIR] --- BoF preparation discussion
Dear community,
In preparation for the BoF on Parallel IR at the US developers meeting
we would like to collect feedback from the whole community. The
concerns, ideas, etc. will be summarized in the BoF and should provide a
good starting point for a discussion.
We know that over the years the topic of a parallel extension for LLVM
was discussed on the mailing list [0, 1, 2], workshops [3, 4] or