search for: verilog

Hello, I wanted to tell the LLVM developers list about http://www.c-to-verilog.com. I created this website to provide free on-line compilation of C into Verilog. I use LLVM as the C parser and optimizer. I have been working on this project for 2 years now. I would like to thank Chris, Vikram and the rest of the LLVM developers. I am very happy with the LLVM infrastructure,...

Hi, For the synthesis backend which translate to VHDL or Verilog, I don't know if I will use LLVM. It will depend on how easy it is to play with concurrent statements with LLVM. For the simulation I will use LLVM because I can anyways artificially make the compiled code sequencial. It would allow me to benefit from all the nice things from LLVM like exi...

If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools). Starting from comparisons to VHDL and Verilog is like designing a new high-level programming language today that is designed to be a better high-level programming language that is supposed to provide better rapid development support than Fortran 7...

Hi, I am working on to implement Scilab codes to FPGA format i.e, a similar kind of c to vhdl by trident compiler.Is there anybody working on this? Regards Manas Das Research Assistant IIT-Bombay -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120919/7eac124e/attachment.html>

folks hi, something i just wanted to double-check. is it possible to use, with LLVM, entirely free software tools to build and upload to a xilinx microblaze FPGA target? i take some c code, put it through llvm-fpga, aaand... then what? is there any documentation about this stuff, anywhere? tia, l.

...ub.com/lbd/index.html It include 10,000 lines of sources code for 1. Step by step, create an llvm backend for the Cpu0 which beginning from a CPU design for school teaching purpose in system programming. 2. ELF linker for Cpu0 which extended from lld. 3. elf2hex extended from llvm-objump. 4. Cpu0 verilog source code. With these code, reader can run the generated code from Cpu0 llvm backend compiler, linker and elf2hex and see how it run on your computer. The pdf and epub is also available in the web. It is a tutorial for llvm backend developer but not for an expert. It is also can be a material...

...fit an old-style GenericValue? I'm wondering if this might be an interim approach that would avoid me needing to rewrite huge amounts of code, and since we're not likely to be supporting anything other than C and C++ in the forseeable future, it makes some sense. Model checking VHDL and Verilog can come later. :-) >> The new GenericValue seems to have morphed into a struct, >> and looks like it's probably not intended to work in the same way as the >> old GenericValue class. >> > > Right. Correspondingly the interpreter code change a fair bit to de...

...lude 10,000 lines of sources code for > > 1. Step by step, create an llvm backend for the Cpu0 which beginning from > a CPU design for school teaching purpose in system programming. > 2. ELF linker for Cpu0 which extended from lld. > 3. elf2hex extended from llvm-objump. > 4. Cpu0 verilog source code. > > With these code, reader can run the generated code from Cpu0 llvm backend > compiler, linker and elf2hex and see how it run on your computer. > The pdf and epub is also available in the web. It is a tutorial for llvm > backend developer but not for an expert. > It...

...-------- TTA-based Co-design Environment (TCE) is a toolset for designing application-specific processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable processor RTL (VHDL and Verilog backends supported) and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network. This release adds support for LLVM 3.1, experimental Verilog backend for the Processor Generator, support for explici...

Hello, I previously sent this message, but it was in HTML only, so it was unreadable. I am thinking about making a compiler for a new HDL language, that will be more modern than VHDL and Verilog and allow a little higher level behavioral description than VHDL. For this language, I am beeing influenced by VHDL, Ada, Ruby and MyHDL. I also would like to write it in Ada. I don't know if it is a project that I will abandon as fast as it popped up in my mind, or not :-) . Anyways, here...

http://www.thekompany.com/embedded/tkcplayer/ Oh yea, it also does some PDA stuff :) __________________________________________________ Do You Yahoo!? Yahoo! Tax Center - online filing with TurboTax http://taxes.yahoo.com/ --- >8 ---- List archives: http://www.xiph.org/archives/ Ogg project homepage: http://www.xiph.org/ogg/ To unsubscribe from this list, send a message to

...GenericValue? I'm > wondering if this might be an interim approach that would avoid me > needing to rewrite huge amounts of code, and since we're not likely to > be supporting anything other than C and C++ in the forseeable future, it > makes some sense. Model checking VHDL and Verilog can come later. :-) Right now, the only interesting thing is 128-bit integers. You can get these on 64-bit targets if you use some funky GCC extensions. Normal code only produces "usual" sized integers. -Chris -- http://nondot.org/sabre/ http://llvm.org/

Hi everybody, I was wondering if there would be interest in having a hardware IP implementing Opus (hardware as in VHDL/Verilog description)? Does that make sense? Several companies that seem to have an interest in Opus (such as Skype, Mozilla, Broadcom, Orange, Huawei) could thus have a dedicated, efficient, low-power solution for phones and tablets. As LTE is being deployed en masse, it would probably be very nice to...

...t include 10,000 lines of sources code for > > 1. Step by step, create an llvm backend for the Cpu0 which beginning from a CPU design for school teaching purpose in system programming. > 2. ELF linker for Cpu0 which extended from lld. > 3. elf2hex extended from llvm-objump. > 4. Cpu0 verilog source code. > > With these code, reader can run the generated code from Cpu0 llvm backend compiler, linker and elf2hex and see how it run on your computer. > The pdf and epub is also available in the web. It is a tutorial for llvm backend developer but not for an expert. > It is also c...

Yes I know, I'm having problems with these tests because they violate the documentation. :) Micah From: Nadav Rotem [mailto:nrotem at apple.com] Sent: Wednesday, October 10, 2012 11:52 AM To: Villmow, Micah Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Inconsistency in the LLVM docs Hi Micah, We need to fix the documentation here. We want to be able to convert vectors of integers to

Hi, Is somewhere alghorithm description of encoder process implemented in libtheora? May be some drafts? May be frame dataflow throw encoder stages? PLEASE -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.xiph.org/pipermail/theora/attachments/20110318/c3e8e109/attachment.htm

...ware (unless you're planning to ship an FPGA as the graphics card, in which case reprogramming is still too slow, and it'll be too expensive). A more accurate approach would be to say, "Well, Mesa is a software implementation of the whole OpenGL stack, right? Why not compile it to verilog using something like c-to-verilog.com (also powered by LLVM) then synthesize that?" The answer is that the resulting code will be far too inefficient to make a useful modern graphics card, and even if it were, you'll have to do lots of work to make it communicate of PCI and DVI, etc. H...

...'m >> wondering if this might be an interim approach that would avoid me >> needing to rewrite huge amounts of code, and since we're not likely to >> be supporting anything other than C and C++ in the forseeable future, it >> makes some sense. Model checking VHDL and Verilog can come later. :-) >> > > Right now, the only interesting thing is 128-bit integers. You can get > these on 64-bit targets if you use some funky GCC extensions. Normal code > only produces "usual" sized integers. > OK, in that case I have a 2 phase plan:...

Not only do FPGAs not support recursion, we don’t even support calls! All user code must be inlined into one kernel/component, which is then used to create HDL for the FPGA. Mark From: Bruce Hoult <brucehoult at sifive.com> Sent: December 17, 2018 9:28 AM To: Mendell, Mark P <mark.p.mendell at intel.com> Cc: jjones at prc-hsv.com; LLVM Developers Mailing List <llvm-dev at

...low-power processor with scratchpad memory, a shift register for inter-lane communication, a hardware sum-reduction tree and predictable performance - you can find details about it at this address: http://users.dcae.pub.ro/~gstefan/2ndLevel/connex.html . The processor has a clean design and its Verilog source code could be made open-source. You can find the source code of the latest version of the compiler (LLVM back end and extensions for Connex in the LoopVectorize module, etc) and runtime I develop for the Connex SIMD processor at this address: https://sites.google.com/site/alexsusu/m...