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2013 Aug 30
4
[LLVMdev] Reflexions about a new HDL language
...lly make the compiled code sequencial. It
would allow me to benefit from all the nice things from LLVM like
existing optimisations. I have never used LLVM, I just read a litlle the
documentation and the tutorial.
Cheers,
Jonas
Le 30. 08. 13 11:24, Óscar Fuentes a écrit :
> Jonas Baggett<jonasb at tranquille.ch> writes:
>
>> What are your feedbacks ?
> Hello Jonas,
>
> How is that related to LLVM? I see no references to LLVM on your
> announcement nor on your document.
2013 Aug 30
0
[LLVMdev] Reflexions about a new HDL language
...rom comparisons to VHDL and Verilog is like designing a new high-level programming language today that is designed to be a better high-level programming language that is supposed to provide better rapid development support than Fortran 77 and C89.
David
On 30 Aug 2013, at 10:43, Jonas Baggett <jonasb at tranquille.ch> wrote:
> Hi,
>
> For the synthesis backend which translate to VHDL or Verilog, I don't know if I will use LLVM. It will depend on how easy it is to play with concurrent statements with LLVM. For the simulation I will use LLVM because I can anyways artificially ma...
2013 Aug 30
2
[LLVMdev] Reflexions about a new HDL language
Hello,
I previously sent this message, but it was in HTML only, so it was
unreadable.
I am thinking about making a compiler for a new HDL language, that will
be more modern than VHDL and Verilog and allow a little higher level
behavioral description than VHDL. For this language, I am beeing
influenced by VHDL, Ada, Ruby and MyHDL. I also would like to write it
in Ada.
I don't know if it
2013 Aug 30
0
[LLVMdev] Reflexions about a new HDL language
Jonas Baggett <jonasb at tranquille.ch> writes:
> What are your feedbacks ?
Hello Jonas,
How is that related to LLVM? I see no references to LLVM on your
announcement nor on your document.
2013 Aug 30
0
[LLVMdev] Some reflexions about a new HDL language
Please don't respond to this thread, since the first message was in HTML
only. Response rather to the thread "Reflexions about a new HDL language".
2013 Sep 18
1
[LLVMdev] Reflexions about a new HDL language
Le 30. 08. 13 11:59, David Chisnall a écrit :
> If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools).
That's a good idea before I go too far , and I think that MyHDL worths a
look too. For Symbolics Processor Designer, I tried
2013 Aug 30
0
[LLVMdev] Some reflexions about a new HDL language