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If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools). Starting from comparisons to VHDL and Verilog is like designing a new high-level programming language today that is designed to be a better high-level programming language that is supposed to provide better rapid development support...

Hi, For the synthesis backend which translate to VHDL or Verilog, I don't know if I will use LLVM. It will depend on how easy it is to play with concurrent statements with LLVM. For the simulation I will use LLVM because I can anyways artificially make the compiled code sequencial. It would allow me to benefit from all the nice things from LLVM like existing optimisations. I have never

...Welcome David Chisnall 1:10 ARM and LLVM Lee Smith 1:30 DOME: Delaying and Overcoming Microprocessor Errors Negar Miralaei 1:50 LLVM to Bluespec Ali Mustafa Zaidi 2:10 CHERI - Language support for hardware capabilities David Chisnall 2:30 TESLA - Temporally Enhanced Security Logic Assertions Jonathan Anderson 2:50 Expl...

Le 30. 08. 13 11:59, David Chisnall a écrit : > If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools). That's a good idea before I go too far , and I think that MyHDL worths a look too. For Symbolics Processor Designer, I tried to find that in google, but I am not sure that I found what you were speaking about. Do you have a l...

On Fri, Sep 20, 2013 at 3:30 AM, Liu Xin <navy.xliu at gmail.com> wrote: > Hi, Akira, > > I found you maintain mips MipsSchedule.td. does it correct? in > MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no > ByPass info out there. > are you sure this reflects the real R4xxx/R5xxx processors. > > why IILoad uses funcition unit ALU? >