llvm dev - Dec 2012 - [LLVMdev] Increase the number of registers in ARM

On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote:
>  The code below in lib/Target/ARM/ARMRegisterInfo.td is where you
> should look into,
> 
> // Integer registers
> def R0  : ARMReg< 0, "r0">,  DwarfRegNum<[0]>;
> def R1  : ARMReg< 1, "r1">,  DwarfRegNum<[1]>;
> 
>  ...
That's the easy part.  ARM (AArch32) has 16 registers because register
operands are stored in a 4-bit bitfield in the instructions.  If you want to add
more registers, then you will also need to modify the instruction encoding of
every instruction, or place them in a separate namespace (as with the NEON / VFP
registers) and add instructions for explicitly modifying them.

David

On Thu, Dec 06, 2012 at 09:13:53AM +0000, David Chisnall
wrote:
> On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote:
> 
> >  The code below in lib/Target/ARM/ARMRegisterInfo.td is where you
> > should look into,
> > 
> > // Integer registers
> > def R0  : ARMReg< 0, "r0">,  DwarfRegNum<[0]>;
> > def R1  : ARMReg< 1, "r1">,  DwarfRegNum<[1]>;
> > 
> >  ...
> 
> That's the easy part.  ARM (AArch32) has 16 registers because register
operands are stored in a 4-bit bitfield in the instructions.  If you want to add
more registers, then you will also need to modify the instruction encoding of
every instruction, or place them in a separate namespace (as with the NEON / VFP
registers) and add instructions for explicitly modifying them.
  Oh, I miss that part. So since the ARM only save 4 bits for register
operand, I don't see there is a easy way to do what you said. Sounds
like a huge work?

Regards,
chenwj
 
-- 
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj

I almost change all the instruction formats. It was a huge work. I am going
to compile and run it now.

Best Regards,
A. Yazdanbakhsh
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
PhD. Student
School of Electrical and Computer Engineering
University of Wisconsin-Madison
E-mail:     yazdanbakhsh at wisc.edu


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On Thu, Dec 6, 2012 at 7:27 PM, 陳韋任 (Wei-Ren Chen) <chenwj at
iis.sinica.edu.tw
> wrote:
> On Thu, Dec 06, 2012 at 09:13:53AM +0000, David Chisnall wrote:
> > On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote:
> >
> > >  The code below in lib/Target/ARM/ARMRegisterInfo.td is where you
> > > should look into,
> > >
> > > // Integer registers
> > > def R0  : ARMReg< 0, "r0">, 
DwarfRegNum<[0]>;
> > > def R1  : ARMReg< 1, "r1">, 
DwarfRegNum<[1]>;
> > >
> > >  ...
> >
> > That's the easy part.  ARM (AArch32) has 16 registers because
register
> operands are stored in a 4-bit bitfield in the instructions.  If you want
> to add more registers, then you will also need to modify the instruction
> encoding of every instruction, or place them in a separate namespace (as
> with the NEON / VFP registers) and add instructions for explicitly
> modifying them.
>
>   Oh, I miss that part. So since the ARM only save 4 bits for register
> operand, I don't see there is a easy way to do what you said. Sounds
> like a huge work?
>
> Regards,
> chenwj
>
> --
> Wei-Ren Chen (陳韋任)
> Computer Systems Lab, Institute of Information Science,
> Academia Sinica, Taiwan (R.O.C.)
> Tel:886-2-2788-3799 #1667
> Homepage: http://people.cs.nctu.edu.tw/~chenwj
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
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