Displaying 3 results from an estimated 3 matches for "50f90b17".
2012 Dec 07
0
[LLVMdev] Increase the number of registers in ARM
On Thu, Dec 06, 2012 at 09:13:53AM +0000, David Chisnall wrote:
> On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote:
>
> > The code below in lib/Target/ARM/ARMRegisterInfo.td is where you
> > should look into,
> >
> > // Integer registers
> > def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
> > def R1 : ARMReg< 1,
2012 Dec 07
2
[LLVMdev] Increase the number of registers in ARM
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> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
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2012 Dec 06
2
[LLVMdev] Increase the number of registers in ARM
On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote:
> The code below in lib/Target/ARM/ARMRegisterInfo.td is where you
> should look into,
>
> // Integer registers
> def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
> def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
>
> ...
That's the easy part. ARM (AArch32) has 16 registers