Displaying 10 results from an estimated 10 matches for "armreg".
2011 Aug 24
1
[LLVMdev] proposal: add macro expansion of for-loop to TableGen
...-----
Notes:
* In statements, you may write #var or #func(args, ...) to expand a
macro or macro function.
* Macro functions are limited to a small set of functions, such as
sequence(), lower(), and upper().
====Example #1====
When defining register files, we repeatedly define every registers. In
ARMRegisterInfo.td:
----------------------------------------
def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>;
def R3 : ARMReg< 3, "r3"...
2012 Dec 06
2
[LLVMdev] Increase the number of registers in ARM
On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote:
> The code below in lib/Target/ARM/ARMRegisterInfo.td is where you
> should look into,
>
> // Integer registers
> def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
> def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
>
> ...
That's the easy part. ARM (AArch32) has 16 regist...
2012 Dec 06
2
[LLVMdev] Increase the number of registers in ARM
Hi,
I want to increase the number of integer registers in the ARM machine.
I don't have any idea how/where I can start. Can anybody help me?
By the way, what are the following line in the ARMRegisterInfo.td specify:
def qsub_0
def qsub_1
....
Thanks
Best Regards,
A. Yazdanbakhsh
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
PhD. Student
School of Electrical and Computer Engineering
U...
2012 Dec 06
0
[LLVMdev] Increase the number of registers in ARM
On Wed, Dec 05, 2012 at 09:17:12PM -0600, Amir Yazdanbakhsh wrote:
> Hi,
>
> I want to increase the number of integer registers in the ARM machine.
> I don't have any idea how/where I can start. Can anybody help me?
The code below in lib/Target/ARM/ARMRegisterInfo.td is where you
should look into,
// Integer registers
def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
...
HTH,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Sci...
2012 Dec 07
0
[LLVMdev] Increase the number of registers in ARM
On Thu, Dec 06, 2012 at 09:13:53AM +0000, David Chisnall wrote:
> On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote:
>
> > The code below in lib/Target/ARM/ARMRegisterInfo.td is where you
> > should look into,
> >
> > // Integer registers
> > def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
> > def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
> >
> > ...
>
> That'...
2012 Mar 21
4
[LLVMdev] apparent mistake in several ports register td file ???
...he field Num seems to have no meaning. It is not recognized by the
backend tools. It does not hurt anything but should not be there.
// We have banks of 32 registers each.
class MipsReg<string n> : Register<n> {
field bits<5> Num;
let Namespace = "Mips";
}
class ARMReg<bits<4> num, string n, list<Register> subregs = []> :
Register<n> {
field bits<4> Num;
let Namespace = "ARM";
let SubRegs = subregs;
// All bits of ARM registers with sub-registers are covered by
sub-registers.
let CoveredBySubRegs = 1;
}
cl...
2012 Mar 29
0
[LLVMdev] apparent mistake in several ports register td file ???
On Mar 21, 2012, at 2:58 PM, reed kotler wrote:
> The field Num seems to have no meaning. It is not recognized by the
> backend tools. It does not hurt anything but should not be there.
>
> class ARMReg<bits<4> num, string n, list<Register> subregs = []> :
> Register<n> {
> field bits<4> Num;
> let Namespace = "ARM";
> let SubRegs = subregs;
> // All bits of ARM registers with sub-registers are covered by
> sub-registers.
> l...
2012 Dec 07
2
[LLVMdev] Increase the number of registers in ARM
...lt;<<
On Thu, Dec 6, 2012 at 7:27 PM, 陳韋任 (Wei-Ren Chen) <chenwj at iis.sinica.edu.tw
> wrote:
> On Thu, Dec 06, 2012 at 09:13:53AM +0000, David Chisnall wrote:
> > On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote:
> >
> > > The code below in lib/Target/ARM/ARMRegisterInfo.td is where you
> > > should look into,
> > >
> > > // Integer registers
> > > def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
> > > def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
> > >
> &g...
2017 Sep 10
2
Question about quad-register
Hi All,
If the target supports quad-register R0:R1:R2:R3 (Rn is 32-bit
register), is it possible mapping quad-register
to v4i32 so that the following example work?
typedef int v4si __attribute__ ((vector_size (16)));
void foo(v4si i) {
v4si j = i;
}
I don't know how to write CallingConv.td to represent the concept of
occupying quad-register R0:R1:R2:R3
once seeing
2012 Mar 23
0
[LLVMdev] apparent mistake in several ports register td file ???
...t recognized by the
> backend tools. It does not hurt anything but should not be there.
>
> // We have banks of 32 registers each.
> class MipsReg<string n> : Register<n> {
> field bits<5> Num;
> let Namespace = "Mips";
> }
>
> class ARMReg<bits<4> num, string n, list<Register> subregs = []> :
> Register<n> {
> field bits<4> Num;
> let Namespace = "ARM";
> let SubRegs = subregs;
> // All bits of ARM registers with sub-registers are covered by
> sub-register...