search for: armregisterinfo

Hi, I want to increase the number of integer registers in the ARM machine. I don't have any idea how/where I can start. Can anybody help me? By the way, what are the following line in the ARMRegisterInfo.td specify: def qsub_0 def qsub_1 .... Thanks Best Regards, A. Yazdanbakhsh >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> PhD. Student School of Electrical and Computer Engineering University...

On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote: > The code below in lib/Target/ARM/ARMRegisterInfo.td is where you > should look into, > > // Integer registers > def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; > def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>; > > ... That's the easy part. ARM (AArch32) has 16 registers becau...

...s. Yep, that's the right way to go. > 2) Line 369 of PPCInstrInfo.td, we declare the non-callee saved registers. > However, Linux and Darwin do not have the same set > of non-callee saved registers. I don't know how to make the if(isDarwin) test > in here Take a look at ARM/ARMRegisterInfo.td for an example of this. > 3) R31, which replaces R1 as stack pointer when there is a dynamic allocation > in a method, must be seen as a callee-saved register and must not be saved > and restored like it is actually for Darwin. I don't know how to specify > that, when there i...

...e: >> 2) Line 369 of PPCInstrInfo.td, we declare the non-callee saved registers. >> However, Linux and Darwin do not have the same set >> of non-callee saved registers. I don't know how to make the if(isDarwin) test >> in here >> > > Take a look at ARM/ARMRegisterInfo.td for an example of this I tried to define Defs just like ARMRegisterInfo.td does with different subtargets, but i get the obvious message: Value 'Defs' of type 'list<Register>' is incompatible with initializer '[{ (the code is at the end of this mail) I'm not sure...

...ould be reachable from all these places in LLVM: - lib/Analysis/ValueTracking.cpp - lib/CodeGen/SelectionDAG/SelectionDAG.cpp - lib/IR/ConstantFold.cpp - lib/Target/ARM/ARMFastISel.cpp - lib/Target/ARM/ARMISelLowering.cpp - lib/Target/ARM/ARMInstrVFP.td (through predicates) - lib/Target/ARM/ARMRegisterInfo.td (through predicates) and in Clang: - lib/AST/ExprConstant.cpp Did I get it right and there is no such flag so far? Does what I'm suggesting sounds reasonable? Thanks, Sergey

Hi, I'm currently working on a register allocation problem. Therefore, I want to reduce the number of available registers of the ARM by a large amount to see the impact on the assembly code. I tried to change the number via the ARMRegisterInfo.td by stripping the registerClasses (like it is described in the Code generator docs), but the resulting code is unchanged. Is there an easy alternative using the registerscavening.cpp directly or did I miss out something?

On Wed, Dec 05, 2012 at 09:17:12PM -0600, Amir Yazdanbakhsh wrote: > Hi, > > I want to increase the number of integer registers in the ARM machine. > I don't have any idea how/where I can start. Can anybody help me? The code below in lib/Target/ARM/ARMRegisterInfo.td is where you should look into, // Integer registers def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>; ... HTH, chenwj -- Wei-Ren Chen (陳韋任) Computer Systems Lab, Institute of Information Science, Aca...

On Thu, Dec 06, 2012 at 09:13:53AM +0000, David Chisnall wrote: > On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote: > > > The code below in lib/Target/ARM/ARMRegisterInfo.td is where you > > should look into, > > > > // Integer registers > > def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; > > def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>; > > > > ... > > That's the eas...

...tests with most of the backends are successful. It turned out that my allocator triggers a specific assertion in the RegScavenger and only for the ARM target. It looks like the LR register is used for frame pointer related things, but it is STILL available for register allocation according to the ARMRegisterInfo.td: def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R12, R11, LR, SP, PC]> Let me now explain the problem step-by-step: 1) Here is the function's mac...

Hi everyone, I have almost completed the implementation of a linux/ppc backend in llvm. There were a few things to modify in lib/Target/PowerPC with a lot of "if (!isDarwin)". There are some places where I need help before saying the port is complete. I attached the diff file as a reference 1) In order to generate a creqv instruction before a vararg call, I created a new

On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: > > > As you can see, PrologEpilogInserter has inserted at the beginning > of the function some code for manipulation of the frame pointer and > this inserted code uses the LR register. > As far as I understand, ARMRegisterInfo.td should exclude the LR > register from the set of allocatable registers for functions that > require frame pointer manipulation. > But currently it is not the case, or? No, LR is not the frame pointer. It's the link register (caller address). It should be available as a general p...

...declare the non-callee saved >>> registers. >>> However, Linux and Darwin do not have the same set >>> of non-callee saved registers. I don't know how to make the if >>> (isDarwin) test >>> in here >>> >> >> Take a look at ARM/ARMRegisterInfo.td for an example of this > I tried to define Defs just like ARMRegisterInfo.td does with > different > subtargets, but i get the obvious > message: > Value 'Defs' of type 'list<Register>' is incompatible with > initializer '[{ > (the code is at th...

...Is this because you want to control the order in which the physical registers are allocated? If so, it'll normally be better to use the TargetRegisterClass::allocation_order_begin() and allocation_order_end() functions to control that. These can be overridden directly in the .td file (see the ARMRegisterInfo.td file for examples) if you want. Other pieces of the compiler also use those iterators to walk the available registers in a register class for local allocation needs, so it's best to keep that logic together (the register scavenger and the anti-dependency breaker, in particular, use them). W...

...gt;: > > On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: > > > As you can see, PrologEpilogInserter has inserted at the beginning > of the function some code for manipulation of the frame pointer and > this inserted code uses the LR register. > As far as I understand, ARMRegisterInfo.td should exclude the LR > register from the set of allocatable registers for functions that > require frame pointer manipulation. > But currently it is not the case, or? > > No, LR is not the frame pointer. It's the link register (caller address). It > should be available as...

...queue new interval. 4) do some work unrelated to these vregs. 5) when selectOrSplit is called again for virtZ it falls through down to the return ~0u line and fails. This issue can be very easily reproduced with the Thumb2 target by doing the following few changes: 1) declare a PTRRC regclass in ARMRegisterInfo.td with only one physreg: def PTRRC : RegisterClass<"ARM", [i32], 32, (add R6)>; 2) modify the RC used in the addr_offset_none addressing mode in ARMInstrInfo.td around line 947 to: let MIOperandInfo = (ops PTRRC:$base); (this is used by the t2LDR_POST instruction) 3) and likewi...

It's not too much of a problem then. I can make a DenseMap between the registers and my registers. It's just one more intermediate step for a lookup. I wish to mimic all the of the registers on the machine with my std::vector<RegisterInfo> RegisterIndexes; vector. Then when a register is used I can assign it easily. I know about alias register and those are taken care of ever so

...7, 2009, at 2:48 AM, Roman Levenstein wrote: >> >> >> As you can see, PrologEpilogInserter has inserted at the beginning >> of the function some code for manipulation of the frame pointer and >> this inserted code uses the LR register. >> As far as I understand, ARMRegisterInfo.td should exclude the LR >> register from the set of allocatable registers for functions that >> require frame pointer manipulation. >> But currently it is not the case, or? >> >> No, LR is not the frame pointer. It's the link register (caller >> address)....

...an Levenstein wrote: >>> >>> >>> As you can see, PrologEpilogInserter has inserted at the beginning >>> of the function some code for manipulation of the frame pointer and >>> this inserted code uses the LR register. >>> As far as I understand, ARMRegisterInfo.td should exclude the LR >>> register from the set of allocatable registers for functions that >>> require frame pointer manipulation. >>> But currently it is not the case, or? >>> >>> No, LR is not the frame pointer. It's the link register (caller &...

Ok, Scratching the surface this morning on Bug 1388. Happy to find that CCR has already been defined in ARMRegisterInfo.td However all uses in the instruction info tablegen files indicate that a two-value operand can't be used where a dag node expects two operands. // FIXME: should be able to write a pattern for ARMBrcond, but can't use // a two-value operand where a dag node expects two operands. :(...

Hi Chris, >> It is marked callee saved. Because when it is not needed as frame >> pointer it is used like an ordinary register. But when it is used as >> frame pointer, the prologue and epilogue change its value, but the >> algorithm in llvm that finds clobbered register does not select it. >> > > Okay, I'm not sure. If you describe the constraints