search for: dwarfregnum

On Jan 9, 2012, at 10:00 AM, Jakob Stoklund Olesen wrote: > > On Jan 8, 2012, at 11:18 PM, Demikhovsky, Elena wrote: > >> I'll explain what we see in the code. >> 1. The caller saves XMM registers across the call if needed (according to DEFS definition). >> YMMs are not in the set, so caller does not take care. > > This is not how the register allocator

...YMM registers on AVX We support Win64, that's right. We defined the upper part of YMM like this // XMM Registers, used by the various SSE instruction set extensions. // Theses are actually only needed for implementing the Win64 CC with AVX. def XMM0b: Register<"xmm0b">, DwarfRegNum<[17, 21, 21]>; def XMM1b: Register<"xmm1b">, DwarfRegNum<[18, 22, 22]>; def XMM2b: Register<"xmm2b">, DwarfRegNum<[19, 23, 23]>; def XMM3b: Register<"xmm3b">, DwarfRegNum<[20, 24, 24]>; def XMM4b: Register<"xmm4...

...;16> Enc, string n, list<Register> subregs> > + : RegisterWithSubRegs<n, subregs> { > let HWEncoding = Enc; > + let Namespace = "BPF"; > + let SubRegIndices = [sub_32]; > } > > -// Integer registers > -def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>; > -def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>; > -def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>; > -def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>; > -def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>; > -def R...

...: Register<n> { field bits<5> Num; let Namespace = "DLX"; } // DLXR - One of the 32 32-bit general-purpose registers class DLXR<bits<5> num, string n> : DLXReg<n> { let Num = num; } // General-purpose registers def R0 : DLXR< 0, "r0">, DwarfRegNum<[0]>; def R1 : DLXR< 1, "r1">, DwarfRegNum<[1]>; def R2 : DLXR< 2, "r2">, DwarfRegNum<[2]>; def R3 : DLXR< 3, "r3">, DwarfRegNum<[3]>; def R4 : DLXR< 4, "r4">, DwarfRegNum<[4]>; def R5 : DLXR<...

...quot;, [i32,f32], 32, (add R0,R1,R2,R3,... def Pair64: RegisterClass<"XYZ", [i64,f64], 64,... (add R0R1, R2R3,... def WideCore : RegisterClass<"XYZ", [i64,f64], 64, (add R0_64, R1_64 ... def R0 : Core<0, "%r0">, DwarfRegNum<[0]>; def R1 : Core<1, "%r1">, DwarfRegNum<[1]>; def R2 : Core<2, "%r2">, DwarfRegNum<[2]>; def R3 : Core<3, "%r3">, DwarfRegNum<[3]>; def R0R1 : CorePair<0,"%r0",[R0,R1] >; def R2R3 : CorePair<2,"%r2&qu...

...* Macro functions are limited to a small set of functions, such as sequence(), lower(), and upper(). ====Example #1==== When defining register files, we repeatedly define every registers. In ARMRegisterInfo.td: ---------------------------------------- def R0  : ARMReg< 0, "r0">,  DwarfRegNum<[0]>; def R1  : ARMReg< 1, "r1">,  DwarfRegNum<[1]>; def R2  : ARMReg< 2, "r2">,  DwarfRegNum<[2]>; def R3  : ARMReg< 3, "r3">,  DwarfRegNum<[3]>; def R4  : ARMReg< 4, "r4">,  DwarfRegNum<[4]>; def R5  : A...

...ectly, Jakob? Having that feature would make a huge difference. I think the for loops have merit, but not the way you want to use them. Some target descriptions have many sequential definitions, for example PowerPC/PPCRegisterInfo.td: // Vector registers def V0 : VR< 0, "v0">, DwarfRegNum<[77, 77]>; def V1 : VR< 1, "v1">, DwarfRegNum<[78, 78]>; ... def V30 : VR<30, "v30">, DwarfRegNum<[107, 107]>; def V31 : VR<31, "v31">, DwarfRegNum<[108, 108]>; Such 'embarrassingly sequential' definitions have no va...

On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote: > The code below in lib/Target/ARM/ARMRegisterInfo.td is where you > should look into, > > // Integer registers > def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; > def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>; > > ... That's the easy part. ARM (AArch32) has 16 registers because register operands are stored in a 4-bit bitfield in the instructions. If you want to add more registers, then you will also need...

...rying to reverse engineer some of the table gen magic around it, but if you or someone readily knows the answer, I would highly appreciate it. Here is the problem. In my back end we have a rather simple int register file structure: // Integer registers. def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>; def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>; def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>; def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>; ... ...which could be accessed as double regs in pairs: // Aliases of the R* registers u...

...d I came across the following problem: as soon as I define two sets of registers that have a many-to-one mapping the live interval pass appears to double- kill the mapped-onto register. I have the following excerpts from my RegisterInfo.td. def V4R0 : R4v<0 , "V4R0 ", []>, DwarfRegNum<0>; def R0 : Rg<0 , "R0", [V4R0]>, DwarfRegNum<0>; def R1 : Rg<1 , "R1", [V4R0]>, DwarfRegNum<1>; when trying to compile: define void @_Z3fooii(i32 %a, i32 %b) { entry: %retval = select i1 false, i32 %a, i32 %b ; <...

> This isn't really my area of expertise, but I think you're messing up > your RegisterClass definition. Look at how ARM defines DTriple. DTriple is untyped :) , because we do not have any valut type which defines 3xi64. However, the paired register needs to have type. Fabian, what are the definitions of ER and DR register classes? -- With best regards, Anton Korobeynikov Faculty

...e data register class def ER : RegisterClass<"TriCore", [i64], 32, (add E0, E2, E4, E6, E8, E10, E12, E14)> { let SubRegClasses = [(DR sub_even, sub_odd)]; } And the DX and EX registers are defined this way: def D0 : TriCoreReg<0, "d0">, DwarfRegNum<[0]>; ... def D15 : TriCoreReg<15, "d15">, DwarfRegNum<[15]>; def E0 : TriCoreRegWithSubregs<0, "e0", [D0, D1]>, DwarfRegNum<[32]>; def E2 : TriCoreRegWithSubregs<2, "e2", [D2, D3]>, DwarfRegNum<[33]>; ... def E14 :...

...table gen magic around it, but if you or > someone readily knows the answer, I would highly appreciate it. > > Here is the problem. > > In my back end we have a rather simple int register file structure: > > // Integer registers. > def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>; > def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>; > def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>; > def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>; > ... > > ...which could be accessed as double regs in pairs: > &...

...llowing problem: as soon as I define two sets of registers > that have a many-to-one mapping the live interval pass appears to > double-kill the mapped-onto register. I have the following excerpts > from my RegisterInfo.td. > > def V4R0 : R4v<0 , "V4R0 ", []>, DwarfRegNum<0>; > > def R0 : Rg<0 , "R0", [V4R0]>, DwarfRegNum<0>; > def R1 : Rg<1 , "R1", [V4R0]>, DwarfRegNum<1>; How are R4v and Rg defined? > > when trying to compile: > > define void @_Z3fooii(i32 %a, i32 %b) { > entry: >...

Hi, I want to increase the number of integer registers in the ARM machine. I don't have any idea how/where I can start. Can anybody help me? By the way, what are the following line in the ARMRegisterInfo.td specify: def qsub_0 def qsub_1 .... Thanks Best Regards, A. Yazdanbakhsh

...I want to increase the number of integer registers in the ARM machine. > I don't have any idea how/where I can start. Can anybody help me? The code below in lib/Target/ARM/ARMRegisterInfo.td is where you should look into, // Integer registers def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>; ... HTH, chenwj -- Wei-Ren Chen (陳韋任) Computer Systems Lab, Institute of Information Science, Academia Sinica, Taiwan (R.O.C.) Tel:886-2-2788-3799 #1667 Homepage: http://people.cs.nctu.edu.tw/~chenwj

Dear all, in my TestRegisterInfo.td file, I defined a register like this: class TestReg<bits<6> enc, string name> : Register<name> { let HWEncoding{5-0} = enc; let Namespace = "TEST"; } def D0 : TestReg<0x01, "d0">, DwarfRegNum<[1]>; but when I compile, the result I have in TestGenAsmMatcher.inc is this: case 'd': // 7 strings to match. switch (Name[1]) { case '0': // 1 string to match. return* 14*; // "d0" I supposed I will get either 1 (because of encoding) or...

..., etc...). So what i did is to define all 8bit regs inside one regclass of size i8 and then define all reg pairs inside another regclass of size i16, marking the pairs as subregs of the 8bit regs this way: <stripped version of my code)> // 8 bit regs def R0 : Register<"r0">, DwarfRegNum<[0]>; def R1 : Register<"r1">, DwarfRegNum<[1]>; // reg pairs def R1R0 : RegisterWithSubRegs<"r0", [R0, R1]>, DwarfRegNum<[0]>; def GPR8 : RegisterClass<"TEST", [i8], 8, [R0, R1]>; def WDREGS : RegisterClass<"TEST", [...

...13:53AM +0000, David Chisnall wrote: > On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote: > > > The code below in lib/Target/ARM/ARMRegisterInfo.td is where you > > should look into, > > > > // Integer registers > > def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; > > def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>; > > > > ... > > That's the easy part. ARM (AArch32) has 16 registers because register operands are stored in a 4-bit bitfield in the instructions. If you want to add more registers,...

...The Mips architecture has register names that are context sensitive. For instance, the 32 general purpose registers for both Mips32 and Mips64 have the same name, but each of the Mips32 registers are just a subregister in their Mips64 instance. def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>; def AT_64 : Mips64GPRReg< 1, "AT", [AT]>; It gets more interesting with floating point where we have 3 different configurations, single precision, double precision aliased with single precision pair and straight double point precision. All of which share the same...