llvm dev - Nov 2012 - [LLVMdev] Undef registers in dependency graph

Hi,
I see that currently physical register uses marked as "undef" can
still
cause dependencies.  Is this intentional?



SU(9):   %D5<def,undef> = LDrid %R0, 0, %R10<imp-def>,
%R11<imp-def>
   # preds left       : 0
   # succs left       : 11
   # rdefs left       : 0
   Latency            : 1
   Depth              : 0
   Height             : 0
   Successors:
    ...
    val SU(14): Latency=1
    val SU(14): Latency=1
    val SU(14): Latency=1
    ...


SU(14):   %D10<def,undef> = HEXAGON_S2_lsl_r_vh %D5<undef>, %R4, 
%R10<imp-use>, %R11<imp-use>, %R20<imp-def>,
%R21<imp-def>;
   # preds left       : 7
   # succs left       : 9
   # rdefs left       : 0
   Latency            : 1
   Depth              : 1
   Height             : 0
   Predecessors:
    val SU(9): Latency=1 Reg=%D5    <-- undef
    val SU(9): Latency=1 Reg=%R10
    val SU(9): Latency=1 Reg=%R11
    ...


-Krzysztof


-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
hosted by The Linux Foundation

Ignore the <def,undef>.  I'm talking about the %D5<undef>.

-K


On 11/1/2012 3:39 PM, Krzysztof Parzyszek wrote:
> Hi,
> I see that currently physical register uses marked as "undef" can
still
> cause dependencies.  Is this intentional?
>
>
>
> SU(9):   %D5<def,undef> = LDrid %R0, 0, %R10<imp-def>,
%R11<imp-def>
>    # preds left       : 0
>    # succs left       : 11
>    # rdefs left       : 0
>    Latency            : 1
>    Depth              : 0
>    Height             : 0
>    Successors:
>     ...
>     val SU(14): Latency=1
>     val SU(14): Latency=1
>     val SU(14): Latency=1
>     ...
>
>
> SU(14):   %D10<def,undef> = HEXAGON_S2_lsl_r_vh %D5<undef>,
%R4,
> %R10<imp-use>, %R11<imp-use>, %R20<imp-def>,
%R21<imp-def>;
>    # preds left       : 7
>    # succs left       : 9
>    # rdefs left       : 0
>    Latency            : 1
>    Depth              : 1
>    Height             : 0
>    Predecessors:
>     val SU(9): Latency=1 Reg=%D5    <-- undef
>     val SU(9): Latency=1 Reg=%R10
>     val SU(9): Latency=1 Reg=%R11
>     ...
>
>
> -Krzysztof
>
>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
hosted by The Linux Foundation

On Nov 1, 2012, at 1:39 PM, Krzysztof Parzyszek <kparzysz at
codeaurora.org> wrote:
> Hi,
> I see that currently physical register uses marked as "undef" can
still cause dependencies.  Is this intentional?
> 
> 
> 
> SU(9):   %D5<def,undef> = LDrid %R0, 0, %R10<imp-def>,
%R11<imp-def>
>  # preds left       : 0
>  # succs left       : 11
>  # rdefs left       : 0
>  Latency            : 1
>  Depth              : 0
>  Height             : 0
>  Successors:
>   ...
>   val SU(14): Latency=1
>   val SU(14): Latency=1
>   val SU(14): Latency=1
>   ...
> 
> 
> SU(14):   %D10<def,undef> = HEXAGON_S2_lsl_r_vh %D5<undef>,
%R4, %R10<imp-use>, %R11<imp-use>, %R20<imp-def>,
%R21<imp-def>;
>  # preds left       : 7
>  # succs left       : 9
>  # rdefs left       : 0
>  Latency            : 1
>  Depth              : 1
>  Height             : 0
>  Predecessors:
>   val SU(9): Latency=1 Reg=%D5    <-- undef
>   val SU(9): Latency=1 Reg=%R10
>   val SU(9): Latency=1 Reg=%R11
>   ...
> 
It looks like the scheduler is overly conservative, but I think you already
worked around it.

I wouldn't mind fixing this, but this isn't really a motivating example.
To handle cases like this, I'd rather just implement tracking of register
unit dependencies.

-Andy