search for: r21

...39;'m trying to install a Debian PV there, and after more than 3 hours it is still installing the base system. I''ve looked at the xenstore backend entries, and everything looks fine: /local/domain/0/backend/qdisk/21/51712/frontend = "/local/domain/21/device/vbd/51712" (n0,r21) /local/domain/0/backend/qdisk/21/51712/params = "aio:/hdd/vm/servlet/servlet.img" (n0,r21) /local/domain/0/backend/qdisk/21/51712/frontend-id = "21" (n0,r21) /local/domain/0/backend/qdisk/21/51712/online = "1" (n0,r21) /local/domain/0/backend/qdisk/21/51712/remo...

...ate10_min1 =  ...... rate10_max1 = ...... ......... so on.   ## ________________________________________________________   # PROBLEM - B   # Suppose Rij = ith Rate and jth range. (There are 3 ranges i.e. j= 3).   data_label = expand.grid(c("R11", "R12", "R13"), c("R21", "R23", "R23"))   # gives the output like     data_label      Var1        Var2 1    R11         R21 2    R12         R21 3    R13         R21 4    R11         R22 5    R12         R22 6    R13         R22 7    R11         R23 8    R12         R23 9    R13         R23      ...

Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place

Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place

...hat the virtual super reg interferes with sub reg instances, even though in reality they shouldn't conflict. That is, they are individual registers and would be better compared as such for register coalescing decisions (CoalescerPair::Partial = 0). For example, I have a super reg that has r20, r21, r22, and r23 physical registers. This super reg is the dest of a reg_sequence which generates 4 COPY MIs. The first COPY coalesces (merging into r20), but the vregs for r21-r23 (SUPER_RC:%vreg50:subreg1..subreg3) are never coalesced after that because doing so generates inteference on %vreg50, the...

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

Hi Borja, > Without doing what i mentioned and letting LLVM expand all operations wider > than 8 bits as you asked, the code produced is excellent supposing that many > of the moves there should be 16 bit moves reducing code size and right > register allocation, also something important for me is that the code is > better than gcc's. When i say right reg allocation it doesnt

...r25:r24 mov r25, r23 mov r24, r22 <-- can be combined into a movw r25:r24, r23:r22 call mcos ; here we have the case i was explaining, pairs dont match because they're the other way round, function result is in r25:r24 ; but it's storing the hi part in r20 instead of r21, so we cant insert a movw mov r20, r25 mov r21, r24 <--- should be mov r21, r25; mov r20, r24 to be able to insert a movw mov r25, r19 mov r24, r18 <-- can be combined into a movw r25:r24, r19:r18 call mcos ; same problem as above, again it's moving the...

This code works: subset(NativeDominant.df,!ID=="37-R17") This code does not: Tree.df<-subset(NativeDominant.df,!ID==c("37-R17","37-R18","10-R1","37-R21","37-R24","R7A-R1","3-R1","37-R16")) how do i get subset() to work on a range of values? -- View this message in context: http://n4.nabble.com/subset-for-multiple-values-tp1560543p1560543.html Sent from the R help mailing list archive at Nabble.com.

...rtual super reg interferes with sub reg instances, even though in reality they shouldn't conflict. That is, they are individual registers and would be better compared as such for register coalescing decisions (CoalescerPair::Partial = 0). > > For example, I have a super reg that has r20, r21, r22, and r23 physical registers. This super reg is the dest of a reg_sequence which generates 4 COPY MIs. The first COPY coalesces (merging into r20), but the vregs for r21-r23 (SUPER_RC:%vreg50:subreg1..subreg3) are never coalesced after that because doing so generates inteference on %vreg50, the...

...# define FAST_REFLECT_CNT # endif @@ -364,7 +363,7 @@ GLOBAL_ENTRY(fast_tick_reflect) mov rp=r29;; mov cr.itm=r26;; // ensure next tick #ifdef FAST_REFLECT_CNT - movl r20=perfcounters+FAST_REFLECT_PERFC_OFS+((0x3000>>8)*4);; + movl r20=PERFC(fast_reflect + (0x3000>>8));; ld4 r21=[r20];; adds r21=1,r21;; st4 [r20]=r21;; @@ -597,7 +596,7 @@ END(fast_break_reflect) // r31 == pr ENTRY(fast_reflect) #ifdef FAST_REFLECT_CNT - movl r22=perfcounters+FAST_REFLECT_PERFC_OFS; + movl r22=PERFC(fast_reflect); shr r23=r20,8-2;; add r22=r22,r23;; ld4 r21=[r22];; @@ -938,7 +9...

...he register allocator to store 16 bit data in two contiguous 8 bit regs being the low part an even reg? Remember data would be expanded into 8 bit ops, so when we're working with dags after type legalization do we really know the original type before expansion? As an example, storing a short in r21:r20 would be valid, but r20:r19 or r20:r18 would be invalid because the in the first case the low reg is odd and in the second case regs arent contiguous. To store data wider than 16 bits, for example for a 32 bit int we would use 2 register pairs (4 8bit regs) but here the pairs dont need to be co...

Hey all, I am trying to work under a State Space form, but I didn't get the help exactly. Have anyone eles used this functions? I was used to work with S-PLUS, but I have some codes I need to adpt. Thanks alot, Bernardo [[alternative HTML version deleted]]

Dear R helpers   Following is a part of R code.   data_lab <- expand.grid(c("R11", "R12", "R13"), c("R21", "R22", "R23"), c("R31", "R32", "R33"), c("R41", "R42", "R43"), c("R51", "R52", "R53"), c("R61", "R62", "R63"), c("R71", "R72", &quot...

...lar type of activity that week). Per the ARIMA instructions I am to feed those in a a vector or matrix. I am getting lost in the sand so to speak at this point. How would I prepare that data? I am pulling from a CSV that is roughly: date,usage,allocation,number of engines, theoretical max,r1,r2,...r21 So far so good just working with a copy of the CSV that is just date,usage But what should I do to disect the configuration data and the r1 to r21 dummy variables? (Some of these explain certain spikes and level shifts, forinstance r21 indicates if there was conversion activity during the week)....

...pth : 0 Height : 0 Successors: ... val SU(14): Latency=1 val SU(14): Latency=1 val SU(14): Latency=1 ... SU(14): %D10<def,undef> = HEXAGON_S2_lsl_r_vh %D5<undef>, %R4, %R10<imp-use>, %R11<imp-use>, %R20<imp-def>, %R21<imp-def>; # preds left : 7 # succs left : 9 # rdefs left : 0 Latency : 1 Depth : 1 Height : 0 Predecessors: val SU(9): Latency=1 Reg=%D5 <-- undef val SU(9): Latency=1 Reg=%R10 val SU(9): Latency=1 Re...

...th NVCC, Ocelot, and LLVM, I can confirm the interleaved instruction schedule with a four-instruction reuse distance. An excerpt follows: . . %r1500 = fmul float %r1496, %r24 ; compute %1500 %r1501 = fmul float %r1497, %r23 %r1502 = fmul float %r1498, %r22 %r1503 = fmul float %r1499, %r21 %r1504 = fmul float %r1500, %r24 ; first use of %1500 %r1505 = fmul float %r1501, %r23 %r1506 = fmul float %r1502, %r22 %r1507 = fmul float %r1503, %r21 %r1508 = fmul float %r1504, %r24 ; first use of %1504 . . The JIT compiler, however, seems to break the interleaving of indepen...

Hi. This patchset implements ia64/pv_ops support which is the framework for virtualization support. Now all the comments so far have been addressed, but only a few exceptions. On x86 various ways to support virtualization were proposed, and eventually pv_ops won. So on ia64 the pv_ops strategy is appropriate too. Later I'll post the patchset which implements xen domU based on ia64/pv_ops.

Hi. This patchset implements ia64/pv_ops support which is the framework for virtualization support. Now all the comments so far have been addressed, but only a few exceptions. On x86 various ways to support virtualization were proposed, and eventually pv_ops won. So on ia64 the pv_ops strategy is appropriate too. Later I'll post the patchset which implements xen domU based on ia64/pv_ops.