Displaying 20 results from an estimated 22 matches for "rdef".
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2012 Nov 01
2
[LLVMdev] Undef registers in dependency graph
Hi,
I see that currently physical register uses marked as "undef" can still
cause dependencies. Is this intentional?
SU(9): %D5<def,undef> = LDrid %R0, 0, %R10<imp-def>, %R11<imp-def>
# preds left : 0
# succs left : 11
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Successors:
...
val SU(14): Latency=1
val SU(14): Latency=1
val SU(14): Latency=1
...
SU(14): %D10<def,undef> = HEXAGON_S2_lsl_r_vh %D5<undef>, %R4,
%R10<imp-use&...
2012 Jun 12
2
[LLVMdev] Latency of true depency of store followed by aliased load in ScheduleDAGInstrs
...ost-RA-sched debug output of the attached ARM example:
$ llc -O3 -debug-only=post-RA-sched store_load_latency_test.ll
...
SU(2): STRi12 %R2<kill>, %R0<kill>, 0, pred:14, pred:%noreg; mem:Volatile ST4[%p1](tbaa=!"int")
# preds left : 1
# succs left : 2
# rdefs left : 0
Latency : 1
Depth : 2
Height : 0
Predecessors:
val SU(1): Latency=1 Reg=%R2
Successors:
antiSU(3): Latency=0
ch SU(3): Latency=0
SU(3): %R0<def> = LDRi12 %R1<kill>, 0, pred:14, pred:%noreg; mem:Volatile LD4[%p2](...
2012 Sep 20
2
[LLVMdev] Scheduling question (memory dependency)
...---------
So far, so good. When we get to list scheduling, not quite so good:
---------------------------------------------------------------
********** List Scheduling **********
SU(0): STH8 %X3<kill>, 162, %X1; mem:ST2[FixedStack-1]
# preds left : 0
# succs left : 4
# rdefs left : 0
Latency : 3
Depth : 0
Height : 0
Successors:
antiSU(2): Latency=0
antiSU(2): Latency=0
ch SU(5): Latency=0
ch SU(4294967295) *: Latency=0
SU(1): %R5<def> = LHA 162, %X1; mem:LD2[%0]
# preds left : 0
# succs...
2013 Mar 19
0
[LLVMdev] setCC and brcond
...addr]> [ORD=1]
0x17f7280: ch = BRcondrel 0x17f8f30, 0x17f7180, 0x17f6b80
0x17f7480: ch = BRrel 0x17f7380, 0x17f7280
********** List Scheduling BB#0 'entry' **********
SU(0): 0x17f7480: ch = BRrel 0x17f7380, 0x17f7280 [ID=0]
# preds left : 1
# succs left : 0
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Predecessors:
ch SU(1): Latency=1
SU(1): 0x17f7280: ch = BRcondrel 0x17f8f30, 0x17f7180, 0x17f6b80 [ID=1]
# preds left : 2
# succs left : 1
# rdefs left : 0
Latency...
2011 Dec 20
2
[LLVMdev] specializing hybrid_ls_rr_sort (was: Re: Bottom-Up Scheduling?)
...choose this fadd over any of the other stores? the
corresponding unit descriptions are:
SU(102): 0x2c03f70: ch = STFSX 0x2c03c70, 0x2bf3910, 0x2c03870,
0x2c03e70<Mem:ST4[%arrayidx6.14](align=8)(tbaa=!"float")> [ORD=94]
[ID=102]
# preds left : 4
# succs left : 1
# rdefs left : 0
Latency : 7
Depth : 0
Height : 0
Predecessors:
val #0x2c11ff0 - SU(105): Latency=3
val #0x2c0cdd0 - SU(32): Latency=1
val #0x2c11db0 - SU(103): Latency=1
ch #0x2c0af70 - SU(5): Latency=0
Successors:
ch #0x2c0ac10 - SU(2)...
2012 Sep 21
0
[LLVMdev] Scheduling question (memory dependency)
...e get to list scheduling, not quite so good:
>
> ---------------------------------------------------------------
> ********** List Scheduling **********
> SU(0): STH8 %X3<kill>, 162, %X1; mem:ST2[FixedStack-1]
> # preds left : 0
> # succs left : 4
> # rdefs left : 0
> Latency : 3
> Depth : 0
> Height : 0
> Successors:
> antiSU(2): Latency=0
> antiSU(2): Latency=0
> ch SU(5): Latency=0
> ch SU(4294967295) *: Latency=0
>
> SU(1): %R5<def> = LHA 162, %...
2012 Sep 21
2
[LLVMdev] Scheduling question (memory dependency)
...e so good:
> >
> > ---------------------------------------------------------------
> > ********** List Scheduling **********
> > SU(0): STH8 %X3<kill>, 162, %X1; mem:ST2[FixedStack-1]
> > # preds left : 0
> > # succs left : 4
> > # rdefs left : 0
> > Latency : 3
> > Depth : 0
> > Height : 0
> > Successors:
> > antiSU(2): Latency=0
> > antiSU(2): Latency=0
> > ch SU(5): Latency=0
> > ch SU(4294967295) *: Latency=0
> &g...
2012 Jun 13
4
[LLVMdev] Assert in live update from MI scheduler.
Andy,
Thanks for reply. I was able to trace the problem to the MI DAG dep
constructor. See this:
SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
# preds left : 0
# succs left : 0
# rdefs left : 1
Latency : 1
Depth : 0
Height : 0
SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg10,%vreg9
# preds left : 0
# succs left : 3
# rdefs left : 1
Latency : 1
De...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
On Jun 12, 2012, at 10:22 AM, Sergei Larin <slarin at codeaurora.org> wrote:
>
> Hello everyone,
>
> I am working on a release based on the branch 3.1 version of code.
> Unfortunately it has enough differences that exact rev does not apply.
> I am hitting an assert in liveness update with seemingly trivial code
> (attached).
>
>
2012 Sep 21
2
[LLVMdev] Scheduling question (memory dependency)
...--------------------------------------------
> > > > ********** List Scheduling **********
> > > > SU(0): STH8 %X3<kill>, 162, %X1; mem:ST2[FixedStack-1]
> > > > # preds left : 0
> > > > # succs left : 4
> > > > # rdefs left : 0
> > > > Latency : 3
> > > > Depth : 0
> > > > Height : 0
> > > > Successors:
> > > > antiSU(2): Latency=0
> > > > antiSU(2): Latency=0
> > > > ch...
2011 Dec 20
0
[LLVMdev] specializing hybrid_ls_rr_sort (was: Re: Bottom-Up Scheduling?)
...? the
> corresponding unit descriptions are:
>
> SU(102): 0x2c03f70: ch = STFSX 0x2c03c70, 0x2bf3910, 0x2c03870,
> 0x2c03e70<Mem:ST4[%arrayidx6.14](align=8)(tbaa=!"float")> [ORD=94]
> [ID=102]
>
> # preds left : 4
> # succs left : 1
> # rdefs left : 0
> Latency : 7
> Depth : 0
> Height : 0
> Predecessors:
> val #0x2c11ff0 - SU(105): Latency=3
> val #0x2c0cdd0 - SU(32): Latency=1
> val #0x2c11db0 - SU(103): Latency=1
> ch #0x2c0af70 - SU(5): Latency=0...
2012 Feb 10
1
[LLVMdev] Question about /llvm/trunk/lib/CodeGen/MachineScheduler.cpp
...vreg194,%vreg185,%vreg187
> To: End Remaining: 0
>
> After ScheduleDAGInstrs::BuildSchedGraph (in AddSchedBarrierDeps
> ExitMI==NULL):
>
> SU(0): %vreg362<def> = COPY %vreg193; IntRegs:%vreg362,%vreg193
> # preds left : 1
> # succs left : 0
> # rdefs left : 1
> Latency : 1
> Depth : 0
> Height : 0
> Predecessors:
> val #0x3fa00e0 - SU(5): Latency=1 Reg=%vreg193
>
> SU(1): %vreg438<def> = COPY %vreg193; IntRegs:%vreg438,%vreg193
> # preds left : 1
> # su...
2012 Sep 21
0
[LLVMdev] Scheduling question (memory dependency)
...> ---------------------------------------------------------------
> > > ********** List Scheduling **********
> > > SU(0): STH8 %X3<kill>, 162, %X1; mem:ST2[FixedStack-1]
> > > # preds left : 0
> > > # succs left : 4
> > > # rdefs left : 0
> > > Latency : 3
> > > Depth : 0
> > > Height : 0
> > > Successors:
> > > antiSU(2): Latency=0
> > > antiSU(2): Latency=0
> > > ch SU(5): Latency=0
> > >...
2017 Aug 12
3
Mischeduler: Unknown reason for peak register pressure increase
I am working on a project where we are integrating an existing pre-RA scheduler into LLVM and we are trying to match our peak register pressure values with the machine instruction schedulers values while using X86. I am finding some mismatches in test cases like the one attached. The registers "AH" and "AL" are live-out but not live-in and I don't see that they are defined
2011 Dec 20
1
[LLVMdev] specializing hybrid_ls_rr_sort (was: Re: Bottom-Up Scheduling?)
...descriptions are:
>>
>> SU(102): 0x2c03f70: ch = STFSX 0x2c03c70, 0x2bf3910, 0x2c03870,
>> 0x2c03e70<Mem:ST4[%arrayidx6.14](align=8)(tbaa=!"float")> [ORD=94]
>> [ID=102]
>>
>> # preds left : 4
>> # succs left : 1
>> # rdefs left : 0
>> Latency : 7
>> Depth : 0
>> Height : 0
>> Predecessors:
>> val #0x2c11ff0 - SU(105): Latency=3
>> val #0x2c0cdd0 - SU(32): Latency=1
>> val #0x2c11db0 - SU(103): Latency=1
>> ch #0x2c...
2012 Sep 21
0
[LLVMdev] Scheduling question (memory dependency)
...-------------------
> > > > > ********** List Scheduling **********
> > > > > SU(0): STH8 %X3<kill>, 162, %X1; mem:ST2[FixedStack-1]
> > > > > # preds left : 0
> > > > > # succs left : 4
> > > > > # rdefs left : 0
> > > > > Latency : 3
> > > > > Depth : 0
> > > > > Height : 0
> > > > > Successors:
> > > > > antiSU(2): Latency=0
> > > > > antiSU(2): Latenc...
2012 Jun 12
2
[LLVMdev] Assert in live update from MI scheduler.
Hello everyone,
I am working on a release based on the branch 3.1 version of code.
Unfortunately it has enough differences that exact rev does not apply.
I am hitting an assert in liveness update with seemingly trivial code
(attached).
/local/mnt/workspace/slarin/tools/llvm-mainline-merged/lib/CodeGen/LiveInter
valAnalysis.cpp:1078: void
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...m MI scheduler.
>
> Andy,
>
> Thanks for reply. I was able to trace the problem to the MI DAG dep
> constructor. See this:
>
> SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
> # preds left : 0
> # succs left : 0
> # rdefs left : 1
> Latency : 1
> Depth : 0
> Height : 0
>
> SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
> IntRegs:%vreg10,%vreg9
> # preds left : 0
> # succs left : 3
> # rdefs...
2018 Sep 20
2
Errononous scheduling of COPY instruction.
...it seems that the Successors of SU(19) is SU(21) and not SU(20) as expected...
What kind of information between the MOV_AB_ro and COPY could be missing?
How to define that the pred of SU(20) should be SU(19)?
SU(19): MOV_AB_ro @s1, %fab_roff0
# preds left : 1
# succs left : 1
# rdefs left : 0
Latency : 0
Depth : 21
Height : 25
Predecessors:
SU(18): Ord Latency=1 Barrier
Successors:
SU(21): Ord Latency=0 Barrier
Pressure Diff :
Single Issue : false;
SU(20): %6:fpuaoffsetclass = COPY %fab_roff0; FPUaO...
2011 Dec 20
0
[LLVMdev] specializing hybrid_ls_rr_sort (was: Re: Bottom-Up Scheduling?)
On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote:
> Here's my "thought experiment" (from PR11589): I have a bunch of
> load-fadd-store chains to schedule. A store takes two cycles to clear
> its last pipeline stage. The fadd takes longer to compute its result
> (say 5 cycles), but can sustain a rate of 1 independent add per cycle.
> As the scheduling is bottom-up, it