search for: r20

Hi, guys, I compiled a subroutine with -O2, and llvm backend produced codes like: ################################################################## LBB0_32: ... R31 = -1 R20 = R31 * R20; .... bnz R2, LBB0_34 LBB0_31: ... b LBB0_34 LBB0_33: # weird basic block? R20 = R5 LBB0_34: .... ################################################################## Wrong answer is produced when executing bove codes. LBB0_33 is not used as des...

...) + ldo 88(%r26),%r19 + fstd,ma %fr12,8(%r19) + fstd,ma %fr13,8(%r19) + fstd,ma %fr14,8(%r19) + fstd,ma %fr15,8(%r19) + fstd,ma %fr16,8(%r19) + fstd,ma %fr17,8(%r19) + fstd,ma %fr18,8(%r19) + fstd,ma %fr19,8(%r19) + fstd,ma %fr20,8(%r19) + fstd %fr21,0(%r19) + bv %r0(%rp) + copy %r0,%r28 + .procend + + .text + .align 4 + .global longjmp + .export longjmp, code + .proc + .callinfo +longjmp: + ldw 0(%r26),%r3 + ldw 8(%r26),%r4 + ldw 12(%r26),%r5 + ldw...

...queue Enabled: Rx Queue count = 1, Tx Queue count = 1 fslinic 0000:01:00.1: Freescale (R) 10 Gigabit Network Connection # insmod fslinicvf.ko Freescale 10 Gigabit PCI Express Network Driver # lspci -mk 00:00.0 "PCI bridge" "Freescale Semiconductor Inc" "Device 0440" -r20 "" "" 01:00.0 "Power PC" "Freescale Semiconductor Inc" "Device 0440" -r20 "" "" 01:00.1 "Power PC" "Freescale Semiconductor Inc" "Device 0440" -r20 "" "" 01:00.4 "Power PC&qu...

...nks that the virtual super reg interferes with sub reg instances, even though in reality they shouldn't conflict. That is, they are individual registers and would be better compared as such for register coalescing decisions (CoalescerPair::Partial = 0). For example, I have a super reg that has r20, r21, r22, and r23 physical registers. This super reg is the dest of a reg_sequence which generates 4 COPY MIs. The first COPY coalesces (merging into r20), but the vregs for r21-r23 (SUPER_RC:%vreg50:subreg1..subreg3) are never coalesced after that because doing so generates inteference on %vreg50...

...egister allocator to store 16 bit data in two contiguous 8 bit regs being the low part an even reg? Remember data would be expanded into 8 bit ops, so when we're working with dags after type legalization do we really know the original type before expansion? As an example, storing a short in r21:r20 would be valid, but r20:r19 or r20:r18 would be invalid because the in the first case the low reg is odd and in the second case regs arent contiguous. To store data wider than 16 bits, for example for a 32 bit int we would use 2 register pairs (4 8bit regs) but here the pairs dont need to be contig...

Hi Borja, > Without doing what i mentioned and letting LLVM expand all operations wider > than 8 bits as you asked, the code produced is excellent supposing that many > of the moves there should be 16 bit moves reducing code size and right > register allocation, also something important for me is that the code is > better than gcc's. When i say right reg allocation it doesnt

...movw r19:r18, r25:r24 mov r25, r23 mov r24, r22 <-- can be combined into a movw r25:r24, r23:r22 call mcos ; here we have the case i was explaining, pairs dont match because they're the other way round, function result is in r25:r24 ; but it's storing the hi part in r20 instead of r21, so we cant insert a movw mov r20, r25 mov r21, r24 <--- should be mov r21, r25; mov r20, r24 to be able to insert a movw mov r25, r19 mov r24, r18 <-- can be combined into a movw r25:r24, r19:r18 call mcos ; same problem as above, again it...

...he virtual super reg interferes with sub reg instances, even though in reality they shouldn't conflict. That is, they are individual registers and would be better compared as such for register coalescing decisions (CoalescerPair::Partial = 0). > > For example, I have a super reg that has r20, r21, r22, and r23 physical registers. This super reg is the dest of a reg_sequence which generates 4 COPY MIs. The first COPY coalesces (merging into r20), but the vregs for r21-r23 (SUPER_RC:%vreg50:subreg1..subreg3) are never coalesced after that because doing so generates inteference on %vreg50...

...libc/arch/parisc/Makefile.inc index 980a543..4fddf5f 100644 --- a/klibc/arch/parisc/Makefile.inc +++ b/klibc/arch/parisc/Makefile.inc @@ -14,6 +14,3 @@ ARCHOBJS = \ ARCHOOBJS = $(patsubst %o,%.lo,%(ARCHOBJS)) archclean: - -arch/$(ARCH)/syscall.o: arch/$(ARCH)/syscall.c - $(CC) $(CFLAGS) -ffixed-r20 -c -o $@ $< diff --git a/klibc/arch/parisc/syscall.S b/klibc/arch/parisc/syscall.S new file mode 100644 index 0000000..a4f26f5 --- /dev/null +++ b/klibc/arch/parisc/syscall.S @@ -0,0 +1,36 @@ +/* + * arch/parisc/syscall.S + * + * %r20 contains the system call number, %r2 contains whence we came...

Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place

Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place

Hello R developers, installing R 2.0.0 from source on a Linux Debian system (gcc 3.2.2) - which worked just fine - I encountered the following problem when trying to update/install packages with the option --with-package-versions: example: RUnit 0.4.0 (also on CRAN) R20 CMD INSTALL -l /mnt/local/R/R-2.0.x-libs-EpiR --with-package-versions RUnit_0.4.0.tar.gz or after untaring R20 CMD INSTALL -l /mnt/local/R/R-2.0.x-libs-EpiR --with-package-versions RUnit I get * Installing *source* package 'RUnit' as 'RUnit_0.4.0' ... ** R ** inst ** save image E...

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

...s := crt0.o targets := crt0.o diff --git a/usr/klibc/arch/parisc/vfork.S b/usr/klibc/arch/parisc/vfork.S new file mode 100644 index 0000000..97ebc8f --- /dev/null +++ b/usr/klibc/arch/parisc/vfork.S @@ -0,0 +1,31 @@ +/* + * arch/parisc/vfork.S, "vfork() me harder. ugh." -- kyle + * + * %r20 contains the system call number, %rp contains whence we came, + * %rp is saved and restored across the syscall, thankfully. + * + */ + + .text + .align 64 ; cache-width aligned + .globl vfork + .type vfork, at function +vfork: + /* pid_t vfork(void) */ + ble 0x100(%sr2, %r0) ; jump to gateway p...

...: 1 Depth : 0 Height : 0 Successors: ... val SU(14): Latency=1 val SU(14): Latency=1 val SU(14): Latency=1 ... SU(14): %D10<def,undef> = HEXAGON_S2_lsl_r_vh %D5<undef>, %R4, %R10<imp-use>, %R11<imp-use>, %R20<imp-def>, %R21<imp-def>; # preds left : 7 # succs left : 9 # rdefs left : 0 Latency : 1 Depth : 1 Height : 0 Predecessors: val SU(9): Latency=1 Reg=%D5 <-- undef val SU(9): Latency=1 Reg=%R10 va...

On Nov 27, 2010, at 8:56 AM, Borja Ferrer wrote: > Some background first: this issue is for a backend for an 8bit microcontroller with only 8bit regs, however it has a few 16bit instructions that only work with fixed register pairs, so it doesnt allow all combinations of regs. This introduces some problems because if data wider than 8bits is expanded into 8bit operations the 16bit instructions

...warfRegNum<[15]>; def R16 : DLXR<16, "r16">, DwarfRegNum<[16]>; def R17 : DLXR<17, "r17">, DwarfRegNum<[17]>; def R18 : DLXR<18, "r18">, DwarfRegNum<[18]>; def R19 : DLXR<19, "r19">, DwarfRegNum<[19]>; def R20 : DLXR<20, "r20">, DwarfRegNum<[20]>; def R21 : DLXR<21, "r21">, DwarfRegNum<[21]>; def R22 : DLXR<22, "r22">, DwarfRegNum<[22]>; def R23 : DLXR<23, "r23">, DwarfRegNum<[23]>; def R24 : DLXR<24, "r24&quo...

...tions(+), 1 deletion(-) diff --git a/usr/klibc/arch/parisc/vfork.S b/usr/klibc/arch/parisc/vfork.S index 97ebc8f..3868a8d 100644 --- a/usr/klibc/arch/parisc/vfork.S +++ b/usr/klibc/arch/parisc/vfork.S @@ -1,7 +1,7 @@ /* * arch/parisc/vfork.S, "vfork() me harder. ugh." -- kyle * - * %r20 contains the system call number, %rp contains whence we came, + * %rp contains whence we came, * %rp is saved and restored across the syscall, thankfully. * */ @@ -12,6 +12,7 @@ .type vfork, at function vfork: /* pid_t vfork(void) */ + ldi 113,%r20 ble 0x100(%sr2, %r0) ; jump to gate...

...0x0000009f r4: 0x00000000 r5: 0x0000009f r6: 0x0000290a r7: 0x726e6f20 r8: 0x66696c65 r9: 0x00000000 r10: 0xbffff78b r11: 0x00000026 r12: 0x8fe71ac7 r13: 0x00000000 r14: 0x000021bc r15: 0x00000000 r16: 0xbffffcb4 r17: 0x00000001 r18: 0x00000000 r19: 0x000016d4 r20: 0x00000000 r21: 0x00000000 r22: 0x00000000 r23: 0x00000000 r24: 0x8fe4b3d8 r25: 0x00000002 r26: 0x00000002 r27: 0x00000000 r28: 0x00001610 r29: 0x00000000 r30: 0x8fe484d8 r31: 0x8fe09ecc