Displaying 1 result from an estimated 1 matches for "hexagon_s2_lsl_r_vh".
2012 Nov 01
2
[LLVMdev] Undef registers in dependency graph
...# preds left : 0
# succs left : 11
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Successors:
...
val SU(14): Latency=1
val SU(14): Latency=1
val SU(14): Latency=1
...
SU(14): %D10<def,undef> = HEXAGON_S2_lsl_r_vh %D5<undef>, %R4,
%R10<imp-use>, %R11<imp-use>, %R20<imp-def>, %R21<imp-def>;
# preds left : 7
# succs left : 9
# rdefs left : 0
Latency : 1
Depth : 1
Height : 0
Predecessors:
val SU(9): Lat...