llvm dev - Oct 2012 - [LLVMdev] Fwd: Debugging/Fixing 'Interval not live at use' errors

On Oct 23, 2012, at 2:10 AM, Stephen McGruer <stephen.mcgruer at
gmail.com> wrote:
> I have a target backend which is currently causing live interval analysis
to throw 'Interval not live at use' errors for many of my benchmarks. I
imagine that this is caused by missing information for my target (probably in
the instructioninfo tablegen?), but I am having difficulties in both debugging
and fixing this problem, and would appreciate any advice or help anyone can
give.
Probably, -verify-machineinstrs will tell you what's wrong.

/jakob

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Hi Stephen,
> I'm not entirely sure what is wrong here - I assume it has something to
do
> with my 'special' instruction LDri_ab. This instruction is a load
with an
> 'address writeback' - ld.ab r0, [r1, 5] is equivalent to ld r0,
[r1]; add
> r1, r1, 5. As it was very difficult to match such behaviour automatically,
I
> actually only generate them manually for prologue/epilogue emission, so the
> tablegen def is like:
That fits. This line

LDri_ab %FP, %SP, 4

should almost certainly be printed as:

%FP = LDri_ab %SP, 4

The most likely cause is a slightly malformed BuildMI that's adding
%FP without a define flag. Usually you put the destination register
inside the call to BuildMI, and inputs with "addReg(...)" and so on.
All this actually does is fiddle the flags in an appropriate manner;
you can emulate it with addReg, but why bother? So what you should be
looking for is something like:

BuildMI(LDri_ab).addReg(Dest).addReg(Src).addImm(Offset)

and changing it to:

BuildMI(LDri_ab, Dest).addReg(Src).addImm(Offset)

Hope this helps.

Tim.

Tim,

Thank you very much, that did indeed fix things. I believe the word I
should be saying is: 'oops'!

Stephen

On 24 October 2012 13:44, Tim Northover <t.p.northover at gmail.com>
wrote:
> Hi Stephen,
>
> > I'm not entirely sure what is wrong here - I assume it has
something to
> do
> > with my 'special' instruction LDri_ab. This instruction is a
load with an
> > 'address writeback' - ld.ab r0, [r1, 5] is equivalent to ld
r0, [r1]; add
> > r1, r1, 5. As it was very difficult to match such behaviour
> automatically, I
> > actually only generate them manually for prologue/epilogue emission,
so
> the
> > tablegen def is like:
>
> That fits. This line
>
> LDri_ab %FP, %SP, 4
>
> should almost certainly be printed as:
>
> %FP = LDri_ab %SP, 4
>
> The most likely cause is a slightly malformed BuildMI that's adding
> %FP without a define flag. Usually you put the destination register
> inside the call to BuildMI, and inputs with "addReg(...)" and so
on.
> All this actually does is fiddle the flags in an appropriate manner;
> you can emulate it with addReg, but why bother? So what you should be
> looking for is something like:
>
> BuildMI(LDri_ab).addReg(Dest).addReg(Src).addImm(Offset)
>
> and changing it to:
>
> BuildMI(LDri_ab, Dest).addReg(Src).addImm(Offset)
>
> Hope this helps.
>
> Tim.
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