I would like to use the LLVM x86 code generator to emit Intel syntax
that is compatible with Microsoft's MASM 9.x. Taking the TOT LLVM, from
last week, I have found a number of changes that are required to make
this work, most of which are straight forward but a couple I wanted to
check with the group to see what people thought was the best thing to
do. In particular, I have made all necessary changes and these are
mostly constrained to the files:
X86IntelAsmPrinter.[h|cpp]
X86TargetAsmInfo.[h|cpp]
Making sure the syntax follows Microsoft MASM requirements.
The main problem that I have hit is regarding the use of CL register in
the shift instructions. The problem is that ATT syntax states that it
should be referenced as "%cl" while Intel says just "cl" but
these
references occur in X86InstInfo.td and this means that it is shared
between Intel and ATT printing! For example, the shift rules:
let Uses = [CL] in {
def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
"shl{b}\t{%cl, $dst|$dst, %CL}",
[(set GR8:$dst, (shl GR8:$src, %CL))]>;
def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
"shl{w}\t{%cl, $dst|$dst, %CL}",
[(set GR16:$dst, (shl GR16:$src, %CL))]>, OpSize;
def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
"shl{l}\t{%cl, $dst|$dst, %CL}",
[(set GR32:$dst, (shl GR32:$src, %CL))]>;
} // Uses = [CL]
Needs to be:
let Uses = [CL] in {
def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
"shl{b}\t{%cl, $dst|$dst, CL}",
[(set GR8:$dst, (shl GR8:$src, CL))]>;
def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
"shl{w}\t{%cl, $dst|$dst, CL}",
[(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
"shl{l}\t{%cl, $dst|$dst, CL}",
[(set GR32:$dst, (shl GR32:$src, CL))]>;
} // Uses = [CL]
The problem is that it does not make sense to have separate rules for
Intel and ATT and as such I wanted to get the lists advice on what
people think is the best approach to resolving this issue so I can make
the changes?
It is also worth noting that MASM does not allow:
shr ESI
to be mean shift by 1 and instead I have to emit:
shr ESI, 1
which I'm assuming is not an issue?
Finally, as far as I can tell from comments on the mailing list the
current Intel syntax emitted by LLVM does not work with any particular
Window's assembler and so making these changes will not cause another
path to stop working, is this correct?
Many thanks,
Ben
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On Mon, Jun 15, 2009 at 5:49 PM, Gaster, Benedict<Benedict.Gaster at amd.com> wrote:> I would like to use the LLVM x86 code generator to emit Intel syntax that is > compatible with Microsoft’s MASM 9.x. Taking the TOT LLVM, from last week, I > have found a number of changes that are required to make this work, most of > which are straight forward but a couple I wanted to check with the group to > see what people thought was the best thing to do. In particular, I have made > all necessary changes and these are mostly constrained to the files: > > > > X86IntelAsmPrinter.[h|cpp] > > X86TargetAsmInfo.[h|cpp]Sounds good; did you mean to attach a patch? It'll be easier to discuss with that. (The output of "svn diff" is fine.)> The main problem that I have hit is regarding the use of CL register in the > shift instructions. The problem is that ATT syntax states that it should be > referenced as “%cl” while Intel says just “cl” but these references occur in > X86InstInfo.td and this means that it is shared between Intel and ATT > printing! For example, the shift rules:We have two different output styles for precisely that reason.> The problem is that it does not make sense to have separate rules for Intel > and ATT and as such I wanted to get the lists advice on what people think is > the best approach to resolving this issue so I can make the changes?The changes just mentioned looks correct.> It is also worth noting that MASM does not allow: > shr ESI > to be mean shift by 1 and instead I have to emit: > shr ESI, 1 > which I’m assuming is not an issue?That's fine.> Finally, as far as I can tell from comments on the mailing list the current > Intel syntax emitted by LLVM does not work with any particular Window’s > assembler and so making these changes will not cause another path to stop > working, is this correct?MASM is about as canonical as it gets for standard Intel syntax, and the changes look reasonable. -Eli
Hi Eli, Thanks for the response I have one question inline. Regards, Ben [...]> The main problem that I have hit is regarding the use of CL registerin the> shift instructions. The problem is that ATT syntax states that itshould be> referenced as "%cl" while Intel says just "cl" but these referencesoccur in> X86InstInfo.td and this means that it is shared between Intel and ATT > printing! For example, the shift rules:We have two different output styles for precisely that reason.> The problem is that it does not make sense to have separate rules forIntel> and ATT and as such I wanted to get the lists advice on what peoplethink is> the best approach to resolving this issue so I can make the changes?The changes just mentioned looks correct. [bg]The problem is I am not sure of the best approach to take here. For example, one possible approach I can see is to following that of the HasSSE2 constraint and introduce something like the follow to X86.td: def IsIntelAsmWriter : Predicate<"Subtarget.isFlavorIntel()">; def IsATTAsmWriter : Predicate<"!Subtarget.isFlavorIntel()">; and then in X86InstrInfo.td make changes something like: def SHL8mCLIntel : I<0xD2, MRM4m, (outs), (ins i8mem :$dst), "shl{b}\t{%cl, $dst|$dst, CL}", [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>, requires<[IsIntelAsmWriter]>; def SHL8mCLATT : I<0xD2, MRM4m, (outs), (ins i8mem :$dst), "shl{b}\t{%cl, $dst|$dst, %CL}", [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>, requires<[IsATTAsmWriter]>; I can get this two work with additional changes to X86InstrInfocpp but the problem I have with this approach is that it introduces a lot of duplication, when all I really want to do is parameterize the final field in the string "shl{b}\t{%cl, $dst|$dst, %CL}". I was wondering (hoping :-) if you knew of a better method to handling this? [...] _______________________________________________ LLVM Developers mailing list LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>On Mon, Jun 15, 2009 at 5:49 PM, Gaster, >Benedict<Benedict.Gaster at amd.com> wrote: >> I would like to use the LLVM x86 code generator to emit Intel syntax that >> is >> compatible with Microsoft’s MASM 9.x. Taking the TOT LLVM, from last >> week, I >> have found a number of changes that are required to make this work, most >> of >> which are straight forward but a couple I wanted to check with the group >> to >> see what people thought was the best thing to do. In particular, I have >> made >> all necessary changes and these are mostly constrained to the files: >> >> X86IntelAsmPrinter.[h|cpp] >> >> X86TargetAsmInfo.[h|cpp] > >Sounds good; did you mean to attach a patch? It'll be easier to >discuss with that. (The output of "svn diff" is fine.)Appently the GAS Intel backend has flaws and does not work correctly anyway so the X86IntelAsm backend is designed only to target MASM anyway. Aaron