Displaying 8 results from an estimated 8 matches for "loadi8".
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loadin
2012 Sep 26
0
[LLVMdev] Folding nodes with more than one use during ISel
...this type of instruction in my InstrInfo.td and the relevant entry for this addressing mode is:
def IdxI16 : IdxPB2Inst<opcode, AddrModeIdxI16, (outs), (ins memsrc:$mem),
!strconcat (str, "\t[$mem]\t; IdxI16"),
[(store (OpNode (loadi8 (loadi16 addrIAny:$mem))),
(loadi16 addrIAny:$mem))>;
where loadi8 and loadi16 are PatFrags that match an i8 and i16 load respectively and OpNode is, in this case, the "not" PatFrag. Pointers are 16-bit by the way.
During instruction selection, this...
2011 Jun 23
0
[LLVMdev] Instr Description Problem of MCore Backend
Hello
> Finally, I don't know how to describe following instructions in
> MCoreInstrInfo.td, because of its variable ins/outs. Or what other files
> should I use to finish this description?
Do you need the isel support for them? If yes, then you should custom
isel them. iirc ARM and SystemZ backends have similar instructions,
while only the first one supports full isel for them. In
2009 Jun 16
2
[LLVMdev] x86 Intel Syntax and MASM 9.x
...avorIntel()">;
def IsATTAsmWriter : Predicate<"!Subtarget.isFlavorIntel()">;
and then in X86InstrInfo.td make changes something like:
def SHL8mCLIntel : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
"shl{b}\t{%cl, $dst|$dst, CL}",
[(store (shl (loadi8 addr:$dst), CL),
addr:$dst)]>, requires<[IsIntelAsmWriter]>;
def SHL8mCLATT : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
"shl{b}\t{%cl, $dst|$dst, %CL}",
[(store (shl (loadi8 addr:$dst), CL),
addr:$dst)]>, requires<[IsATTAsmWriter]>;
I can get this t...
2009 Jun 16
0
[LLVMdev] x86 Intel Syntax and MASM 9.x
On Mon, Jun 15, 2009 at 5:49 PM, Gaster,
Benedict<Benedict.Gaster at amd.com> wrote:
> I would like to use the LLVM x86 code generator to emit Intel syntax that is
> compatible with Microsoft’s MASM 9.x. Taking the TOT LLVM, from last week, I
> have found a number of changes that are required to make this work, most of
> which are straight forward but a couple I wanted to check
2009 Jun 16
3
[LLVMdev] x86 Intel Syntax and MASM 9.x
I would like to use the LLVM x86 code generator to emit Intel syntax
that is compatible with Microsoft's MASM 9.x. Taking the TOT LLVM, from
last week, I have found a number of changes that are required to make
this work, most of which are straight forward but a couple I wanted to
check with the group to see what people thought was the best thing to
do. In particular, I have made all necessary
2011 Jun 23
2
[LLVMdev] Instr Description Problem of MCore Backend
Hi, all:
Now I'm working on writing a backend for Moto MCore, but I don't know how to
describe some instructions.
First, I've already written MCoreRegisterInfo.td like these:
class MCoreReg<bits<4> num, string name> : Register<name> {
let Namespace = "MCore";
field bits<4> Num = num;
}
def R0 : MCoreReg< 0, "R0">,
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
...10, "load", OpInfo_F64, II_LOAD1 >;
defm LOADI32 : LoadOp< 0b1001010, "load", OpInfo_I32, II_LOAD1 >;
defm LOADF32 : LoadOp< 0b1001010, "load", OpInfo_F32, II_LOAD1 >;
defm LOADI16 : LoadOp< 0b1001010, "load", OpInfo_I16, II_LOAD1 >;
defm LOADI8 : LoadOp< 0b1001010, "load", OpInfo_I8, II_LOAD1 >;
I tried replacing 'load' with 'LOADI64' in the patter, like this:
def: Pat<(LOADI64 (XSTGADDR_NORMAL tglobaladdr:$addr)),
(LOADI64 tglobaladdr:$addr, 0)>;
But that resulted in:
XSTGInstrPatterns...
2016 Jan 13
2
Expanding a PseudoOp and accessing the DAG
On Wed, Jan 13, 2016 at 2:08 PM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 1/13/2016 2:26 PM, Phil Tomson via llvm-dev wrote:
>
>> I've got this PseudoOp defined:
>>
>> def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>]>;
>> def XSTGRELADDR :