search for: mrm4m

...introduce something like the follow to X86.td: def IsIntelAsmWriter : Predicate<"Subtarget.isFlavorIntel()">; def IsATTAsmWriter : Predicate<"!Subtarget.isFlavorIntel()">; and then in X86InstrInfo.td make changes something like: def SHL8mCLIntel : I<0xD2, MRM4m, (outs), (ins i8mem :$dst), "shl{b}\t{%cl, $dst|$dst, CL}", [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>, requires<[IsIntelAsmWriter]>; def SHL8mCLATT : I<0xD2, MRM4m, (outs), (ins i8mem :$dst), "shl{b}\t{%cl, $dst|$dst, %CL}", [...

On Mon, Jun 15, 2009 at 5:49 PM, Gaster, Benedict<Benedict.Gaster at amd.com> wrote: > I would like to use the LLVM x86 code generator to emit Intel syntax that is > compatible with Microsoft’s MASM 9.x. Taking the TOT LLVM, from last week, I > have found a number of changes that are required to make this work, most of > which are straight forward but a couple I wanted to check

I would like to use the LLVM x86 code generator to emit Intel syntax that is compatible with Microsoft's MASM 9.x. Taking the TOT LLVM, from last week, I have found a number of changes that are required to make this work, most of which are straight forward but a couple I wanted to check with the group to see what people thought was the best thing to do. In particular, I have made all necessary

Vladimir Prus wrote: > On my target, the multiplication can involve all general purpose registers, > but there's are still some restrictions: the first and the second operand > as well as the result must be in different registers, and neither register > can be gr7. How can I enforce this restriction on the register allocator? And the other side of the question is now to inform

On my target, the multiplication can involve all general purpose registers, but there's are still some restrictions: the first and the second operand as well as the result must be in different registers, and neither register can be gr7. How can I enforce this restriction on the register allocator? - Volodya

...gister()) { > - if (isX86_64ExtendedReg(MO)) > - REX |= 1 << Bit; > - Bit++; > - } > - } > - break; > - } > - case X86II::MRM0m: case X86II::MRM1m: > - case X86II::MRM2m: case X86II::MRM3m: > - case X86II::MRM4m: case X86II::MRM5m: > - case X86II::MRM6m: case X86II::MRM7m: > - case X86II::MRMDestMem: { > - unsigned e = isTwoAddr ? 5 : 4; > - i = isTwoAddr ? 1 : 0; > - if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e))) > - REX |= 1 << 2; &...

OK, here's a new patch that adds the infrastructure and the implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize. Both functions are virtual functions defined in TargetInstrInfo.h. For X86, I moved some commodity functions from X86CodeEmitter to X86InstrInfo. What do you think? Nicolas Evan Cheng wrote: > > I think both of these belong to TargetInstrInfo. And

...[]>; +let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in + def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*} $dst # TAILCALL", + []>; +let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp\t{*}$dst # TAIL CALL", []>; Please fix the inconsistency: "TAILCALL" vs. "TAIL CALL". +SDOperand GetPossiblePreceedingTailCall(SDOperand Chain) { This should be "static"? + + Chain = DAG.getNode(...

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