search for: lvgv

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2011 Dec 13
0
[LLVMdev] AMD IL Code Generator Backend for OpenCL
...ween kernels and non-kernels. `triple.ll' in your patch has this metadata, but I can't see how to construct it with clang.. %0 = type { i8*, i8*, i8*, i8*, i32 } @sgv = internal addrspace(2) constant [1 x i8] zeroinitializer @fgv = internal addrspace(2) constant [1 x i8] zeroinitializer @lvgv = internal constant [0 x i8*] zeroinitializer @llvm.global.annotations = appending global [1 x %0] [%0 { i8* bitcast (void ()* @__OpenCL_foo_kernel to i8*), i8* bitcast ([1 x i8] addrspace(2)* @sgv to i8*), i8* bitcast ([1 x i8] addrspace(2)* @fgv to i8*), i8* bitcast ([0 x i8*]* @lvgv to i8*), i32...
2011 Dec 13
2
[LLVMdev] AMD IL Code Generator Backend for OpenCL
We are working on getting the documentation cleaned up to the point where it can be released. If you look at the test cases, you can infer what needs to be done. Basically since this is targeted for OpenCL, we annotate OpenCL kernels slightly different than normal functions and that is what causes the code to be generated. That being said, on my list of things to do is fix this so that any
2009 Jun 16
0
[LLVMdev] x86 Intel Syntax and MASM 9.x
On Mon, Jun 15, 2009 at 11:21 PM, Gaster, Benedict<Benedict.Gaster at amd.com> wrote: > I can get this two work with additional changes to X86InstrInfocpp but > the problem I have with this approach is that it introduces a lot of > duplication, when all I really want to do is parameterize the final > field in the string "shl{b}\t{%cl, $dst|$dst, %CL}". I was wondering
2009 Jun 16
2
[LLVMdev] x86 Intel Syntax and MASM 9.x
Hi Eli, Thanks for the response I have one question inline. Regards, Ben [...] > The main problem that I have hit is regarding the use of CL register in the > shift instructions. The problem is that ATT syntax states that it should be > referenced as "%cl" while Intel says just "cl" but these references occur in > X86InstInfo.td and this means that it is shared
2009 Jun 16
5
[LLVMdev] x86 Intel Syntax and MASM 9.x
...; 0x3 dd __2E_str db 12 dup(0) dd 7 ; 0x7 dd 3 ; 0x3 dd __2E_str1 db 12 dup(0) db 12 dup(0) sgv: ; sgv db 1 dup(0) ALIGN 4 lvgv: ; lvgv ALIGN 32 foo: ; dq 4589156319577832937 ; double value: 6.241881e-002 dq 4589442480094401190 ; double value: 6.630889e-002 MASM reports the following error: error A2189:invalid combination with s...
2010 Sep 29
0
[LLVMdev] spilling & xmm register usage
...:64-v128:128:128-a0:0:64-f80:128:128" > > %0 = type { i8*, i8*, i8*, i8*, i32 } > %1 = type { float addrspace(1)*, i32, float addrspace(1)*, float addrspace(1)* } > > @sgv = internal constant [1 x i8] zeroinitializer > @fgv = internal constant [1 x i8] zeroinitializer > @lvgv = internal constant [0 x i8*] zeroinitializer > > declare float @llvm.sqrt.f32(float) nounwind readonly > > declare float @llvm.exp.f32(float) nounwind readonly > > declare float @llvm.log.f32(float) nounwind readonly > > declare float @fabs(float) > > define void...
2010 Sep 29
3
[LLVMdev] spilling & xmm register usage
Hello everybody, I have stumbled upon a test case (the attached module is a slightly reduced version) that shows extremely reduced performance on linux compared to windows when executed using LLVM's JIT. We narrowed the problem down to the actual code being generated, the source IR on both systems is the same. Try compiling the attached module: llc -O3 -filetype=asm -o BAD.s BAD.ll Under