Displaying 3 results from an estimated 3 matches for "isattasmwriter".
2009 Jun 16
2
[LLVMdev] x86 Intel Syntax and MASM 9.x
...t.
[bg]The problem is I am not sure of the best approach to take here. For
example, one possible approach I can see is to following that of the
HasSSE2 constraint and introduce something like the follow to X86.td:
def IsIntelAsmWriter : Predicate<"Subtarget.isFlavorIntel()">;
def IsATTAsmWriter : Predicate<"!Subtarget.isFlavorIntel()">;
and then in X86InstrInfo.td make changes something like:
def SHL8mCLIntel : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
"shl{b}\t{%cl, $dst|$dst, CL}",
[(store (shl (loadi8 addr:$dst), CL),
addr:$dst)]>, r...
2009 Jun 16
0
[LLVMdev] x86 Intel Syntax and MASM 9.x
On Mon, Jun 15, 2009 at 5:49 PM, Gaster,
Benedict<Benedict.Gaster at amd.com> wrote:
> I would like to use the LLVM x86 code generator to emit Intel syntax that is
> compatible with Microsoft’s MASM 9.x. Taking the TOT LLVM, from last week, I
> have found a number of changes that are required to make this work, most of
> which are straight forward but a couple I wanted to check
2009 Jun 16
3
[LLVMdev] x86 Intel Syntax and MASM 9.x
I would like to use the LLVM x86 code generator to emit Intel syntax
that is compatible with Microsoft's MASM 9.x. Taking the TOT LLVM, from
last week, I have found a number of changes that are required to make
this work, most of which are straight forward but a couple I wanted to
check with the group to see what people thought was the best thing to
do. In particular, I have made all necessary