llvm dev - Mar 2007 - [LLVMdev] Live intervals and aliasing registers problem

I'm having trouble with overlapping intervals for vector registers.  
How are intervals for registers that both alias to the same larger  
register intended to be handled?

To demonstrate this problem you can use a minor addition to the Sparc  
register description.

Add this to the SparcRegisterInfo.td at line 68:

// Rtest
class Rtest<bits<5> num, string n, list<Register> aliases> :  
SparcReg<n> {
   let Num = num;
   let Aliases = aliases;
}

def ALIASING : Rtest<0, "Rtest0", [I0, I1]>,
DwarfRegNum<0>;

Then attempt to build the attached llvm file using 'llvm-as <  
vecinterval.ll | llc -debug -march=sparc vecinterval -f -o  
vecinterval.s'

I get the following error:
********** COMPUTING LIVE INTERVALS **********
********** Function: _Z3fooff
entry:
                 livein register: I0 killed +[0,2:0)
                 livein register: Rtest0 killed +[0,2:0)
                 livein register: I1 killed +[0,6:0)
                 livein register: Rtest0 killed +[0,2:1)
lib/CodeGen/LiveInterval.cpp:189: failed assertion `B->end <= Start  
&& "Cannot overlap two LiveRanges with differing ValID's"
" (did you
def the same reg twice in a MachineInstr?)"'
Abort trap



--
Christopher Lamb
christopher.lamb at gmail.com

-------------- next part --------------
A non-text attachment was scrubbed...
Name: vecinterval.ll
Type: application/octet-stream
Size: 417 bytes
Desc: not available
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20070326/1a95f9a2/attachment.obj>
-------------- next part --------------