search for: sparcregisterinfo

Chris Lattner wrote: > This is probably a difference between the sun and GNU assemblers. > There is no current sparc maintainer, so feel free to change it if one > way works better for you. Hi Chris, Here's the fix: Index: SparcRegisterInfo.cpp =================================================================== --- SparcRegisterInfo.cpp (revision 700) +++ SparcRegisterInfo.cpp (working copy) @@ -137,7 +137,7 @@ if (NumBytes >= -4096) { BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri), - SP::O6).addImm...

On Jul 31, 2008, at 9:57 AM, Dale Johannesen wrote: > > On Jul 31, 2008, at 4:52 AMPDT, Richard Pennington wrote: > >> Any code that I generate for the Sparc fails at assembly time using a >> gas assembler built for the Sparc. >> >> I get code like the following from the code generator: >> >> save -96, %o6, %o6 >> >> and get a syntax

Hi, guys. I was browsing through SparcRegisterInfo.td, and I did not find support for quad-precision floating-point registers, that is, a single register of 128 bits aliasing four registers of 32. As this is predicted in the Sparc V8 manual (http://www.sparc.org/standards/V8.pdf, page 33), do you guys plan on adding this feature? all the best,...

I'm having trouble with overlapping intervals for vector registers. How are intervals for registers that both alias to the same larger register intended to be handled? To demonstrate this problem you can use a minor addition to the Sparc register description. Add this to the SparcRegisterInfo.td at line 68: // Rtest class Rtest<bits<5> num, string n, list<Register> aliases> : SparcReg<n> { let Num = num; let Aliases = aliases; } def ALIASING : Rtest<0, "Rtest0", [I0, I1]>, DwarfRegNum<0>; Then attempt to build the attached llvm fi...

...be/build/./lib/Target/X86/MCTargetDesc/Release+Asserts/X86MCTargetDesc.o differ: byte 159231, line 159 ./lib/Target/Sparc/Release+Asserts/SparcISelDAGToDAG.o ../../recurse2be/build/./lib/Target/Sparc/Release+Asserts/SparcISelDAGToDAG.o differ: byte 25814, line 106 ./lib/Target/Sparc/Release+Asserts/SparcRegisterInfo.o ../../recurse2be/build/./lib/Target/Sparc/Release+Asserts/SparcRegisterInfo.o differ: byte 16949, line 12 ./lib/Target/Sparc/InstPrinter/Release+Asserts/SparcInstPrinter.o ../../recurse2be/build/./lib/Target/Sparc/InstPrinter/Release+Asserts/SparcInstPrinter.o differ: byte 26716, line 14 ./lib/Ta...

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...(*thisMBB, MI, DL, TII->get(SP::STri)) + .addReg(BufReg) + .addImm(3 * PtrSize) + .addReg(SP::I7); + MIB.setMemRefs(MMOBegin, MMOEnd); + + + // Setup + MIB = BuildMI(*thisMBB, MI, DL, TII->get(SP::BCOND)).addMBB(mainMBB).addImm(SPCC::ICC_A); + const SparcRegisterInfo* TRI = Subtarget->getRegisterInfo(); + MIB.addRegMask(TRI->getNoPreservedMask()); + + BuildMI(thisMBB, DL, TII->get(SP::LDri)) + .addReg(restoreDstReg, RegState::Define) + .addImm(1) + .addReg(SP::G0); + + MIB = BuildMI(*thisMBB, MI, DL, TII-...