Displaying 3 results from an estimated 3 matches for "sparcreg".
2012 Mar 21
4
[LLVMdev] apparent mistake in several ports register td file ???
...quot;ARM";
let SubRegs = subregs;
// All bits of ARM registers with sub-registers are covered by
sub-registers.
let CoveredBySubRegs = 1;
}
class ARMFReg<bits<6> num, string n> : Register<n> {
field bits<6> Num;
let Namespace = "ARM";
}
class SparcReg<string n> : Register<n> {
field bits<5> Num;
let Namespace = "SP";
}
Then subsequently, further derived types copy the mistake.
// Registers are identified with 5-bit ID numbers.
// Ri - 32-bit integer registers
class Ri<bits<5> num, string n> : Sp...
2012 Mar 23
0
[LLVMdev] apparent mistake in several ports register td file ???
...ts of ARM registers with sub-registers are covered by
> sub-registers.
> let CoveredBySubRegs = 1;
> }
>
> class ARMFReg<bits<6> num, string n> : Register<n> {
> field bits<6> Num;
> let Namespace = "ARM";
> }
>
> class SparcReg<string n> : Register<n> {
> field bits<5> Num;
> let Namespace = "SP";
> }
>
>
>
>
> Then subsequently, further derived types copy the mistake.
>
> // Registers are identified with 5-bit ID numbers.
> // Ri - 32-bit integer reg...
2007 Mar 27
0
[LLVMdev] Live intervals and aliasing registers problem
I'm having trouble with overlapping intervals for vector registers.
How are intervals for registers that both alias to the same larger
register intended to be handled?
To demonstrate this problem you can use a minor addition to the Sparc
register description.
Add this to the SparcRegisterInfo.td at line 68:
// Rtest
class Rtest<bits<5> num, string n, list<Register> aliases> :
SparcReg<n> {
let Num = num;
let Aliases = aliases;
}
def ALIASING : Rtest<0, "Rtest0", [I0, I1]>, DwarfRegNum<0>;
Then attempt to build the attache...