search for: livein

...___________ From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] on behalf of Tom Stellard [thomas.stellard at amd.com] Sent: Friday, February 03, 2012 1:55 PM To: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [PATCH] MachineRegisterInfo: Don't emit the same livein copy more than once On Fri, Jan 27, 2012 at 02:56:03PM -0500, Tom Stellard wrote: > --- > > Is MachineRegisterInfo::EmitLiveInCopies() only meant to be called once > per compile? If I call it more than once, it emits duplicate copies > which causes the live interval analysis to fai...

On Mon, Feb 13, 2012 at 10:17:11PM -0800, Lang Hames wrote: > Hi Tom, > > I'm pretty sure this function should only ever be called once, by > SelectionDAG. Do you know where the second call is coming from in your code? > > Cheers, > Lang. Hi Lang, I was calling EmitLiveInCopies() from one of my backend specific passes. If the function can only be called once, then I'll just try to merge that pass with into the SelectionDAG. Thanks, Tom > > On Mon, Feb 13, 2012 at 7:03 PM, Stellard, Thomas <Tom.Stellard at amd.com>wrote: > > > This patch...

...mmits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] > on behalf of Tom Stellard [thomas.stellard at amd.com] > Sent: Friday, February 03, 2012 1:55 PM > To: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] [PATCH] MachineRegisterInfo: Don't emit the > same livein copy more than once > > On Fri, Jan 27, 2012 at 02:56:03PM -0500, Tom Stellard wrote: > > --- > > > > Is MachineRegisterInfo::EmitLiveInCopies() only meant to be called once > > per compile? If I call it more than once, it emits duplicate copies > > which causes...

Hi all, Is there a pass that computes livein information for each MachineBasicBlock? I tried to find such a pass but could not find any. I am trying to use the livein information to get dead registers to insert some instructions right before code emission but the livein information seems to be invalidated by some pass. I might need to rec...

Hi Tom, As far as I can tell EmitLiveInCopies is just there to handle physreg arguments and return values. Is there any reason for these to change late in your backend? - Lang. On Tue, Feb 14, 2012 at 7:22 AM, Tom Stellard <thomas.stellard at amd.com>wrote: > On Mon, Feb 13, 2012 at 10:17:11PM -0800, Lang Hames wrote: > &...

I would like to maintain the livein information for physical registers on basic blocks past register allocation, or recreate it if possible. The goal is to be able to run a late pass of DeadMachineInstrElim, which requires valid livein information. The X86 target returns false for requiresRegisterScavenging so passes like BranchFold...

...LLVM BB @0x8501b00, ID#0): %reg1024 = ORI %R0, 0 %reg1025 = ORI %R1, 0 RETL Machine Function ********** REWRITING TWO-ADDR INSTRS ********** ********** Function: _Z3fooff ********** COMPUTING LIVE INTERVALS ********** ********** Function: _Z3fooii entry: livein register: R0 killed +[0,2:0) livein register: V4R0 killed +[0,2:0) livein register: R1 killed +[0,6:0) livein register: V4R0 killed +[0,2:1) lib/CodeGen/LiveInterval.cpp:189: failed assertion `B->end <= Start && "Cannot overl...

...ORI %R0, 0 > %reg1025 = ORI %R1, 0 > RETL > Machine Function > ********** REWRITING TWO-ADDR INSTRS ********** > ********** Function: _Z3fooff > > ********** COMPUTING LIVE INTERVALS ********** > ********** Function: _Z3fooii > entry: > livein register: R0 killed +[0,2:0) > livein register: V4R0 killed +[0,2:0) <=== this > is bad > livein register: R1 killed +[0,6:0) > livein register: V4R0 killed +[0,2:1) > lib/CodeGen/LiveInterval.cpp:189: failed assertion `B->en...

Thanks -- View this message in context: http://llvm.1065342.n5.nabble.com/is-liveIns-in-machineBasicBlock-only-valid-for-first-block-in-machine-function-tp63667.html Sent from the LLVM - Dev mailing list archive at Nabble.com.

...behaviour with llvm-2.6. This would have spared saving/restoring r11. Although this is not a functionnal regression, this looks to me like a performance regression, unless the calling convention has changed (i.e. the arguments can not be clobbered anymore). I have not yet understood why, but the liveIntervals analysis dump looks dubious to me (R12W,R13W,R14W and R15W should be dead/killed livein registers) : > llc -march=msp430 -debug-only=liveintervals -o test_unused_regs.s test_unused_regs.ll ********** COMPUTING LIVE INTERVALS ********** ********** Function: test BB#0: # derived from...

...ORI %R1, 0 >> RETL >> Machine Function >> ********** REWRITING TWO-ADDR INSTRS ********** >> ********** Function: _Z3fooff >> >> ********** COMPUTING LIVE INTERVALS ********** >> ********** Function: _Z3fooii >> entry: >> livein register: R0 killed +[0,2:0) >> livein register: V4R0 killed +[0,2:0) <=== this >> is bad >> livein register: R1 killed +[0,6:0) >> livein register: V4R0 killed +[0,2:1) >> lib/CodeGen/LiveInterval.cpp:189: failed...

...<def> = LDR <fi#0>, %reg0, 0, 14, %reg0 >>>> %SP<def> = ADDri %SP<kill>, 4, 14, %reg0, %reg0 >>>> BX_RET 14, %reg0 >>> >>> Ok, ignore my earlier email about BX_RET. The issue is LR should be added >>> to >>> livein of BB #1. >> >> Who should do it? >> Do you mean that ARM backend/LiveIntervalsAnalysis/LiveVariables >> should do it or do you mean that my regalloc should do it? > > Register allocator should update mbb Livein info. OK. >> >> >>> **** Post Mach...

Adds code to have DCE start off with a list of physical registers to be live on entry to at least one successor basic block (as mentioned in the FIXME comment). -- Sanjoy Das http://playingwithpointers.com -------------- next part -------------- A non-text attachment was scrubbed... Name: FIXME.patch Type: text/x-diff Size: 899 bytes Desc: not available URL:

On Jun 21, 2011, at 12:51 AM, Sanjoy Das wrote: > Adds code to have DCE start off with a list of physical registers to be > live on entry to at least one successor basic block (as mentioned in the > FIXME comment). Looks good, but keep the comment (sans FIXME).

...(4,4) >> [0x8fc2d68 + 0] >> %LR<def> = LDR <fi#0>, %reg0, 0, 14, %reg0 >> %SP<def> = ADDri %SP<kill>, 4, 14, %reg0, %reg0 >> BX_RET 14, %reg0 > > Ok, ignore my earlier email about BX_RET. The issue is LR should be added to > livein of BB #1. Who should do it? Do you mean that ARM backend/LiveIntervalsAnalysis/LiveVariables should do it or do you mean that my regalloc should do it? > **** Post Machine Instrs **** > # Machine code for Insert(): > Live Ins: R0 in VR#1025 R1 in VR#1026 > > entry: 0x8fdac90, LLVM...

...gt;>> %LR<def> = LDR <fi#0>, %reg0, 0, 14, %reg0 >>> %SP<def> = ADDri %SP<kill>, 4, 14, %reg0, %reg0 >>> BX_RET 14, %reg0 >> >> Ok, ignore my earlier email about BX_RET. The issue is LR should be >> added to >> livein of BB #1. > > Who should do it? > Do you mean that ARM backend/LiveIntervalsAnalysis/LiveVariables > should do it or do you mean that my regalloc should do it? Register allocator should update mbb Livein info. > > >> **** Post Machine Instrs **** >> # Machine code fo...

On Jan 14, 2010, at 6:39 PM, 任坤 wrote: > But I want do some optimization after register alloction by adjusting > register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. You can also look at RegisterScavenging.cpp and MachineVerifier.cpp. They are doing the same

...rfRegNum<0>; Then attempt to build the attached llvm file using 'llvm-as < vecinterval.ll | llc -debug -march=sparc vecinterval -f -o vecinterval.s' I get the following error: ********** COMPUTING LIVE INTERVALS ********** ********** Function: _Z3fooff entry: livein register: I0 killed +[0,2:0) livein register: Rtest0 killed +[0,2:0) livein register: I1 killed +[0,6:0) livein register: Rtest0 killed +[0,2:1) lib/CodeGen/LiveInterval.cpp:189: failed assertion `B->end <= Start && "Cannot ove...

Is there an easy way to obtain all liveout variables of a basic block? Liveins can be found for each MachineBasicBlock, but I can only find liveouts for the whole function, at MachineRegisterInfo. Do I need to find them out manually?

Hi, I have ported LLC to a risc cpu. It can pass benchmark that I have at current. But I want do some optimization after register alloction by adjusting register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. R4 is marked <kill> at MBB0. If I scan R4's