llvm dev - Aug 2006 - [LLVMdev] need some help to remove a dummy mov

I have just added a retflag to the ARM backend. I thought that using
BRIND directly was to blame for a dummy move. But I the move wasn't
removed.

When compiling
---------------------------------------
int %g() {
entry:
        call void %f( )
        ret int 42
}

declare void %f()
--------------------------------------

The ARM backend produces
-------------------------------------------
g:
        sub r13, r13, #4
        str r14, [r13]
        mov r4, #42
        bl f
        mov r0, r4
        ldr r14, [r13, #0]
        add r13, r13, #4
        bx r14
------------------------------------------

It would be better to do a "mov r0, #42" directly. The isel dag is
almost identical to the one generated for ppc32, but on ppc32 "li r3,
42" is used.

I have checked that isMoveInstr returns true for the "mov r0,r 4".

Does someone has any idea why the additional mov is generated?

Thanks,
Rafael

On Thu, 3 Aug 2006, [UTF-8] Rafael Esp?ndola wrote:
> It would be better to do a "mov r0, #42" directly. The isel dag
is
> almost identical to the one generated for ppc32, but on ppc32 "li r3,
> 42" is used.
>
> I have checked that isMoveInstr returns true for the "mov r0,r
4".
> Does someone has any idea why the additional mov is generated?
This looks like a scheduling problem.  Looking at the -print-machineinstrs 
dump, the input to the register allocator looks like this:

# Machine code for g():
Live Outs: R0

entry (0x8b030c0, LLVM BB @0x8b00350):
         %reg1024 = movri 42
         ADJCALLSTACKDOWN 4
         bl <ga:f>
         ADJCALLSTACKUP 4
         %R0 = movrr %reg1024
         bx

The problem is that 'bl' clobbers R0/R1/R2/R3, so "reg1024"
can't get any
of those.  As such, it gets allocated to R4.

If you use one of the 'register pressure reducing' schedulers, you get 
good code, e.g.:

$ llvm-as < t.ll | llc -march=arm -sched=list-burr


         .text
         .globl  g
         .align  2
g:
         sub r13, r13, #4
         str r14, [r13]
         bl f
         mov r0, #42
         ldr r14, [r13, #0]
         add r13, r13, #4
         bx r14

To default to "reducing register pressure", add this:

   setSchedulingPreference(SchedulingForRegPressure);

to your ARMTargetLowering ctor, like the X86 backend has.

-Chris

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