search for: setschedulingpreference

...e -pre-RA-sched option anywhere >> other than on the command line for the provided tools. So what code >> would I write (or where is the API?) to change the pre-regalloc >> instruction scheduler algorithm? > > Does this thing below in TargetLowering help? > > /// setSchedulingPreference - Specify the target scheduling preference. > void setSchedulingPreference(SchedPreference Pref) Thanks! That doesn't look like what -pre-RA-sched eventually maps to, but it looks like the switch I want to change. Pardon my ignorance, but I have no idea how I'm supposed to get to...

Sorry for responding to my own message but I would really appreciate some help with this. Looking through the documentation again this morning I noticed that setSchedulingPreference is a protected method of LLVMTargetLowering, so it looks like it's not something I can call directly anyway. Furthermore it's only called from one place with a hard-coded value for any particular platform. Andrew Andrew Friedley wrote: > Sanjiv Gupta wrote: >> On Wed, 2010-04-...

...n't figure out how to set the -pre-RA-sched option anywhere > other than on the command line for the provided tools. So what code > would I write (or where is the API?) to change the pre-regalloc > instruction scheduler algorithm? Does this thing below in TargetLowering help? /// setSchedulingPreference - Specify the target scheduling preference. void setSchedulingPreference(SchedPreference Pref) - Sanjiv > I've been unable to find this in the documentation or reading source > code; a pointer would be really useful. > > Thanks, > > Andrew > _______________________...

I've found that I need to set the -pre-RA-sched parameter when using tools like llc to get the kind of instruction scheduling I want. However I'm normally generating and running code on the fly using the JIT, and can't figure out how to set the -pre-RA-sched option anywhere other than on the command line for the provided tools. So what code would I write (or where is the API?) to

Hi Andrew, On 04/19/10 14:27, Andrew Friedley wrote: > Sorry for responding to my own message but I would really appreciate > some help with this. > > Looking through the documentation again this morning I noticed that > setSchedulingPreference is a protected method of LLVMTargetLowering, so > it looks like it's not something I can call directly anyway. > Furthermore it's only called from one place with a hard-coded value for > any particular platform. > > Andrew Friedley wrote: > >> Sanjiv Gupta wrot...

...ay to ensure the PPC scheduling isn't hosed now or in the future is probably to make it work as much like ARM as possible. This means (1) defaulting to the "hybrid" scheduler, (2) implementing the register pressure limit, and (3) reenabling the hazard recognizer. (1) TargetLowering::setSchedulingPreference(Sched::Hybrid) (2) TargetRegisterInfo::getRegisterPressureLimit(...) should probably return something a bit less than 32, depending on register class. (3) The standard hazard recognizer works either bottom-up or top-down on the itinerary data. So it *should* work out-of-box. The problem is that P...

...heduler() -> true and enableMachineSchedDefaultSched() -> true, this has no effect of course. But just to be clear what the future is, I'd suggest to change it too. :) After this step, out-of-tree targets could still have "enableMachineScheduler()" return false, and call "setSchedulingPreference(Sched::ILP)" (or whatever other option), if they want to keep using the old scheduler after this step, until step 3 happens. Step 2: Wait for some time to pass, for people to notice performance regressions, or otherwise complain. Step 3: Delete all the selectiondag scheduling code, the above...

...g isn't hosed now or in the > future is probably to make it work as much like ARM as possible. > > This means (1) defaulting to the "hybrid" scheduler, (2) implementing the > register pressure limit, and (3) reenabling the hazard recognizer. > > (1) TargetLowering::setSchedulingPreference(Sched::Hybrid) > > (2) TargetRegisterInfo::getRegisterPressureLimit(...) should probably > return something a bit less than 32, depending on register class. > > (3) The standard hazard recognizer works either bottom-up or top-down > on the itinerary data. So it *should* work out...

Is there documentation somewhere for the bottom-up scheduling? I'm trying to figure out what changes are necessary in order to support it in the PPC backend. Thanks in advance, Hal On Thu, 2011-10-20 at 10:21 -0700, Evan Cheng wrote: > > On Oct 19, 2011, at 7:29 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > > Evan, > > > > Thanks for the heads up! Is

...iner, I removed RegisterScheduler::setDefault in r243388. It was used to override the default command line option that selects the DAG scheduler to use. Instead of hacking into the command line plumbing, a target that wants more control over the selection of the scheduler than it already has with setSchedulingPreference has a SubTargetHook “getDAGScheduler” that can be overridden. The original motivation for this change was to remove some mutable global state. — Mehdi -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150728...

I have just added a retflag to the ARM backend. I thought that using BRIND directly was to blame for a dummy move. But I the move wasn't removed. When compiling --------------------------------------- int %g() { entry: call void %f( ) ret int 42 } declare void %f() -------------------------------------- The ARM backend produces ------------------------------------------- g:

I'm a taking a compiler course and I'm supposed to implement a scheduler for the LLVM compiler and comapre its persformance to the existing one used by LLVM-gcc. I need some help understanding what is really happening in LLVM-gcc. In CodeGen/SelectionDAG/ I can see four different Schedulers, which one is used by LLVM? Can you give a hint on where/how to add a new scheduler and test

...Scheduler. According to the brief documentation in the source file ScheduleDAGRRList, the BURR is a register pressure reduction scheduler, while the ILP is a register-pressure aware scheduler that tries to balance ILP and register pressure. Yes. For those wondering how to find out, grep for 'setSchedulingPreference'. > My questions are: > > -Are there any references (such as published research) that describe each/any of these scheduling algorithms? The LLVM ILP scheduler is a mix of heuristics, some of which may be standard practice while others are LLVM inventions. The combination of heurist...

Hi, I am currently writing a paper documenting a research project that we have done on pre-allocation instruction scheduling to balance ILP and register pressure. In the paper we compare the pre-allocation scheduler that we have developed to LLVM's default schedulers for two targets: x86-64 and x86-32. We would like to include in our paper some brief descriptions of the two LLVM

...er. According to the brief documentation in the source file ScheduleDAGRRList, the BURR is a register pressure reduction scheduler, while the ILP is a register-pressure aware scheduler that tries to balance ILP and register pressure. > Yes. For those wondering how to find out, grep for 'setSchedulingPreference'. My questions are: > > >-Are there any references (such as published research) that describe each/any of these scheduling algorithms?  The LLVM ILP scheduler is a mix of heuristics, some of which may be standard practice while others are LLVM inventions. The combination of heuristic...

...e > > future is probably to make it work as much like ARM as possible. > > > > This means (1) defaulting to the "hybrid" scheduler, (2) implementing the > > register pressure limit, and (3) reenabling the hazard recognizer. > > > > (1) TargetLowering::setSchedulingPreference(Sched::Hybrid) > > > > (2) TargetRegisterInfo::getRegisterPressureLimit(...) should probably > > return something a bit less than 32, depending on register class. > > > > (3) The standard hazard recognizer works either bottom-up or top-down > > on the itinerary...

.... According to the brief documentation in the source file ScheduleDAGRRList, the BURR is a register pressure reduction scheduler, while the ILP is a register-pressure aware scheduler that tries to balance ILP and register pressure. > > Yes. For those wondering how to find out, grep for 'setSchedulingPreference'. > >> My questions are: >> >> -Are there any references (such as published research) that describe each/any of these scheduling algorithms? > > The LLVM ILP scheduler is a mix of heuristics, some of which may be standard practice while others are LLVM inventions....

...the brief documentation in the source file ScheduleDAGRRList, the BURR is a register pressure reduction scheduler, while the ILP is a register-pressure aware scheduler that tries to balance ILP and register pressure. >> > > >Yes. For those wondering how to find out, grep for 'setSchedulingPreference'. > > >My questions are: >> >> >>-Are there any references (such as published research) that describe each/any of these scheduling algorithms?  > > >The LLVM ILP scheduler is a mix of heuristics, some of which may be standard practice while others are LLVM in...