search for: retflag

I have changed the way in which the ARM backend generates a function return. Instead of expanding a RET to a CopyToReg;RETFLAG, it now expands into a CopyToReg;BRIND. I haven't commit it yet, but the patch is attached. In my opinion the resulting code is easier to understand, but I have some questions: Why all backends use RETFLAG? Why it is named RETFLAG? Why the Copy that places the result must have a Flag operan...

I am trying to make the ARM backend compile int f() {return 0;} I have added a custom expansion of ret that is similar to the one used in ppc and sparc. If I understand it correctly, it will expand the ret into an assignment to the return register (R0) and a RETFLAG node. I declared the bx instruction to match RETFLAG. Now the instruction selection says it can't match " i32 = Constant <0>" I tried to declare a fake mov that is capable of moving arbitrary i32 constants to a register (ops IntRegs:$dst, i32imm:$src). But the error is still...

On Tue, 30 May 2006, [UTF-8] Rafael Esp?ndola wrote: > I have changed the way in which the ARM backend generates a function > return. Instead of expanding a RET to a CopyToReg;RETFLAG, it now > expands into a CopyToReg;BRIND. I haven't commit it yet, but the patch > is attached. Ok, I haven't looked at the code, but you're free to do whatever make sense. > In my opinion the resulting code is easier to understand, but I have > some questions: > >...

...the problem. > Do you know how to debug this, or do you want me to give you basic directions? I had a look at the matcher table and it looks as follows: /*4309*/ /*Scope*/ 12, /*->4322*/ /*4310*/ OPC_CheckOpcode, TARGET_VAL(MBPISD::RET_FLAG), /*4313*/ OPC_RecordNode, // #0 = 'retflag' chained node /*4314*/ OPC_CaptureGlueInput, /*4315*/ OPC_EmitMergeInputChains1_0, /*4316*/ OPC_MorphNodeTo, TARGET_VAL(MyTarget::RETL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic0, 0/*#VTs*/, 0/*#Ops*/, // Src: (retflag) - Complexity = 3 // Dst:...

...#39;t. Here's the pattern: > > let isTerminator = 1, isBarrier = 1, noResults = 1 in { > let isReturn = 1 in { > def RET: BRForm<0b00010101100, (ops), > "bi $$lr", > BranchResolv, > [(retflag)]>; > } > } > > Output from make: > > llvm[0]: Building SPU.td code emitter with tblgen > tblgen: /work/scottm/llvm/utils/TableGen/CodeGenInstruction.h:118: > std::pair<unsigned int, unsigned int> > llvm::CodeGenInstruction::getSubOperandNumber(unsigned int) co...

...t; Yep, $$ should work. It doesn't. Here's the pattern: let isTerminator = 1, isBarrier = 1, noResults = 1 in { let isReturn = 1 in { def RET: BRForm<0b00010101100, (ops), "bi $$lr", BranchResolv, [(retflag)]>; } } Output from make: llvm[0]: Building SPU.td code emitter with tblgen tblgen: /work/scottm/llvm/utils/TableGen/CodeGenInstruction.h:118: std::pair<unsigned int, unsigned int> llvm::CodeGenInstruction::getSubOperandNumber(unsigned int) const: Assertion `i < OperandList.size() &...

On Tue, 9 Jan 2007, Evan Cheng wrote: >> - How does one deal with multiple instruction sequences in a pattern? >> To load a constant is a two instruction sequence, but both >> instructions only take two operands (assume that r3 is a 32-bit >> register): >> >> ilhu $3, 45 # r3 = (45 << 16) >> iohl $3, 5 # r3 |= 5

Hi Quentin, >> Yes, the dags in view-isel-dags and view-legalize-types-dags are correct (the add operations are here and are their results are used) and the dags are the same. > > And what about view-sched-dags? The DAG looks like I described below (*) > This one should give you what has been selected. So if this is not correct, you have indeed a problem in the selection

Is there any way to add an optional flag edge to a BRIND node? I In the ARM backend I lower returns directly to BRINDs, so I need to add an edge connecting the BRIND and the CopyToReg that sets the return value. The other option is to create an ARM specific node that is identical to BRIND except for having a flag edge. Thanks, Rafael

I have just added a retflag to the ARM backend. I thought that using BRIND directly was to blame for a dummy move. But I the move wasn't removed. When compiling --------------------------------------- int %g() { entry: call void %f( ) ret int 42 } declare void %f() --------------------------------------...

...r a given def? For example I have a following instruction definition in the .td file let isReturn = 1, isTerminator = 1, hasDelaySlot=1, isBarrier = 1, isCodeGenOnly = 1, Inst = 0x44004800 in { def RET : InstBR<0x1, (outs), (ins), "l.jr\tr9", [(retflag)]>; } Ultimately when I track it down the def tracks down to class Instruction in include/llvm/Target/Target.td, ie. class Instruction { string Namespace = ""; dag OutOperandList; // An dag containing the MI def operand list. dag InOperandList; // An dag containin...

> > Why it is named RETFLAG? > > Historical reason. Originally we didn't have nodes that could > *optionally* have an input flag. A better design, e.g. on PPC would be to > have a PPCISD::RET node, which takes an optional input flag, and always > lower RET to it. I See. I will try to always lower to &quot...