similar to: [LLVMdev] need some help to remove a dummy mov

I have changed the way in which the ARM backend generates a function return. Instead of expanding a RET to a CopyToReg;RETFLAG, it now expands into a CopyToReg;BRIND. I haven't commit it yet, but the patch is attached. In my opinion the resulting code is easier to understand, but I have some questions: Why all backends use RETFLAG? Why it is named RETFLAG? Why the Copy that places the

On Tue, 30 May 2006, [UTF-8] Rafael Esp?ndola wrote: > I have changed the way in which the ARM backend generates a function > return. Instead of expanding a RET to a CopyToReg;RETFLAG, it now > expands into a CopyToReg;BRIND. I haven't commit it yet, but the patch > is attached. Ok, I haven't looked at the code, but you're free to do whatever make sense. > In my

Hi, I'd like to understand how register allocation works in the case where an instruction is folded into another one. Where in the code would be a good place to start looking at? After ISEL, one of the instructions has another instruction folded into it, which looks like this t1: i32,i1,i1,i1,i1 = ADDRR TargetFrameIndex:i32<0>, MOVRI:i32,i1,i1 But during the 'Assembly

On Wed, 9 Jun 2004, Vladimir Prus wrote: > Chris Lattner wrote: > > > Thanks, this works! I don't yet understand why spill code is needed there > > > at all, but I'll return to that when I have branches working correctly. > > > > I'm not sure either. Can you send the code before and after register > > allocation? > > Attached. Okay, yeah

Chris Lattner wrote: > > Thanks, this works! I don't yet understand why spill code is needed there > > at all, but I'll return to that when I have branches working correctly. > > I'm not sure either. Can you send the code before and after register > allocation? Attached. > You might also try -regalloc=linearscan, as the default > allocator is, uhhh,

I've tried to implement the isMoveInstr method from TargetInstrInfo class, and the register allocator immediately started to crash, in: #4 0x40e88787 in llvm::LiveIntervals::joinIntervals (this=0x80630b0) at ../lib/CodeGen/LiveIntervals.cpp:493 493 assert(r2iA != r2iMap_.end()); The instruction it crashes is: (gdb) p $4.dump() %reg1056 = move %gr7 And gr7 is

On Thu, 2004-07-01 at 09:26, Vladimir Prus wrote: > I've tried to implement the isMoveInstr method from TargetInstrInfo class, and > the register allocator immediately started to crash, in: > > #4 0x40e88787 in llvm::LiveIntervals::joinIntervals (this=0x80630b0) > at ../lib/CodeGen/LiveIntervals.cpp:493 > 493 assert(r2iA != r2iMap_.end()); >

I am trying to make the ARM backend compile int f() {return 0;} I have added a custom expansion of ret that is similar to the one used in ppc and sparc. If I understand it correctly, it will expand the ret into an assignment to the return register (R0) and a RETFLAG node. I declared the bx instruction to match RETFLAG. Now the instruction selection says it can't match " i32 = Constant

VLIW (Very Long Instruction Word) is a long instruction format (called "group" hereafter) contains several instructions. These instructions are not dependent on each other and could be issued in a single cycle. At this moment there is no correspondent class for VLIW. MachineInstr object can only represent one instruction. Usually the number of instructions in a group is fixed. The

On Tue, 9 Jan 2007, Evan Cheng wrote: >> - How does one deal with multiple instruction sequences in a pattern? >> To load a constant is a two instruction sequence, but both >> instructions only take two operands (assume that r3 is a 32-bit >> register): >> >> ilhu $3, 45 # r3 = (45 << 16) >> iohl $3, 5 # r3 |= 5

While adding support for branch instructions in my backend, I run into a trouble. The code to handle branches looks like: void visitBranchInst(BranchInst& BI) { BB->addSuccessor (MBBMap[BI.getSuccessor(0)]); if (BI.isConditional()) BB->addSuccessor (MBBMap[BI.getSuccessor(1)]); ........... BuildMI(BB,

Chris Lattner wrote: > On Tue, 8 Jun 2004, Vladimir Prus wrote: > > While adding support for branch instructions in my backend, I run into a > > trouble. The code to handle branches looks like: > > The machine code after instruction selection is: > > > > entry (0x8681458): > > %reg1024 = load <fi#-1> > > %reg1025 = load

On Wed, 9 Jun 2004, Vladimir Prus wrote: > > I assume that the two unconditional gotos are just test code, right? If > > not, the second one is dead. > > Yes, in the final form there will be "iflt" instruction before the first goto, > making it conditional. Ah, ok :) > > > The code after "goto" is disturbing. It looks like spill code, but

On Mon, 25 Jul 2005, Tzu-Chien Chiu wrote: > But please allow me to explain the hardware in detail. Hope there is > more elegant way to solve it. Sounds good! > The hardware is a "stream processor". That is, It processes samples > one by one. Each sample is associated with several 128-bit > four-element vector registers, namely: > > * input registers - the

Hi Quentin, Am 03.11.2014 um 23:30 schrieb Quentin Colombet <qcolombet at apple.com>: >> Continuing at 4309 >> Match failed at index 4310 >> Continuing at 4322 >> Morphed node: 0x7fef2a033610: i32 = MVrr 0x7fef2a033610 [ORD=21] >> >> >> Does the add operation become a MOVE instruction, or is this a chain of rules? > > Yes, your add becomes

Evan, thanks for responding so quickly. On Tuesday 26 June 2007 14:11, Evan Cheng wrote: > On Jun 26, 2007, at 11:20 AM, David A. Greene wrote: > > 28 %AL<dead> = MOV8rr %reg1024<kill>, %EAX<imp-def> > > MOV8rr %mreg(2)<d> %reg1024 %mreg(17)<d> > > 32 CALL64pcrel32 <ga:printf>, %RDI<kill>, %RAX<imp-def>, %RCX<imp- > >

On Mar 27, 2007, at 3:25 PM, Evan Cheng wrote: > > On Mar 25, 2007, at 7:12 AM, Christopher Lamb wrote: > >> While beginning to add vector registers to a back end I came >> across the following problem: as soon as I define two sets of >> registers that have a many-to-one mapping the live interval pass >> appears to double-kill the mapped-onto register. I

For the x86-64 target, I tried compiling a simple hello world. I don't understand the live interval information. Here's the machine instructions as dumped by LiveIntervalAnalysis: ********** MACHINEINSTRS ********** file hello.c line 3 b: 0 FNSTCW16m <fi#0>, 1, %NOREG, 0 FNSTCW16m <fi#0> 1 %mreg(0) 0 4 MOV8mi <fi#0>, 1, %NOREG, 1, 2 MOV8mi <fi#0> 1 %mreg(0) 1 2 8

It seems to me that LLVM sub-register is not for the following hardware architecture. All instructions of a hardware are vector instructions. All registers contains 4 32-bit FP sub-registers. They are called r0.x, r0.y, r0.z, r0.w. Most instructions write more than one elements in this way: mul r0.xyw, r1, r2 add r0.z, r3, r4 sub r5, r0, r1 Notice that the four elements of r0 are written

Hi, I'd like to understand the order in which patterns are searched during ISEL. In the example below, indices are searched in ascending order from 808 to 3305, then it goes back to 3259 and eventually it matches the wrong instruction. Why did go back from 3305 to 3259? In my XXXGenDAGISel.inc, I can see that the correct instruction is at index 3420 but it never got there. ISEL: Starting