search for: movri

...allocation works in the case where an instruction is folded into another one. Where in the code would be a good place to start looking at? After ISEL, one of the instructions has another instruction folded into it, which looks like this t1: i32,i1,i1,i1,i1 = ADDRR TargetFrameIndex:i32<0>, MOVRI:i32,i1,i1 But during the 'Assembly Printer' pass, when emitting the assembly for ADDRR, the assertion at the beginning of getRegisterName() in XXXGenAsmWriter.inc fails because RegNo is 0. I'd like to know how that happened. Thanks. -------------- next part -------------- An HTML atta...

...index 514, continuing at 559 Skipped scope entry (due to false predicate) at index 560, continuing at 605 Skipped scope entry (due to false predicate) at index 606, continuing at 651 Skipped scope entry (due to false predicate) at index 652, continuing at 685 Morphed node: 0x17f6d80: i32 = MOVri 0x17f8f30 [ORD=4] ISEL: Match complete! ===== Instruction selection ends: Selected selection DAG: BB#2 'isZero:if.else' SelectionDAG has 5 nodes: 0x17f8f30: i32 = TargetConstant<0> 0x17f6b80: i32 = TargetFrameIndex<0> 0x17f8f30: <multiple use> 0x17f8f30:...

...he opcode %a,%b,immediate general form. Clearly I also need a way to load a 32 bit constant value into a register in order to be able to address more than 64K of memory. I know the PPC does something similar ... So for example for SABRE this instruction output would perform the necessary ... MOVri %a, HI16(32 bit constant) LSHri %a,16 ORri %a, LO16(same 32 bit constant) LD %d, %a // ie load the contents of the memory at the address stored in %a into register %d where the HI/LO16 are performed at code generation by LLVM. I'm a little confused as to how to specify this as a pattern in t...

Is it possible to get a virtual register and then use that to create a real register? I've seen it done in unittests/CodeGen/MachineInstrTest.cpp like this: unsigned VirtualDef1 = -42; VD1VU->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); But when I do that in my code I get an assertion so I wasn't sure if it's legal or not. Thanks.

Hi Tim, >That C++ function is probably what looks for an FrameIndex node and >has been taught that it can be folded into the load. How do you teach a function that a node can be folded into an instruction? ________________________________ From: Tim Northover <t.p.northover at gmail.com> Sent: Monday, January 21, 2019 11:52 PM To: Josh Sharp Cc: via llvm-dev Subject: Re: [llvm-dev]

I have just added a retflag to the ARM backend. I thought that using BRIND directly was to blame for a dummy move. But I the move wasn't removed. When compiling --------------------------------------- int %g() { entry: call void %f( ) ret int 42 } declare void %f() -------------------------------------- The ARM backend produces ------------------------------------------- g:

On Wed, Jun 26, 2019 at 12:38 PM Tim Northover <t.p.northover at gmail.com> wrote: > Hi Gleb, > > On Wed, 26 Jun 2019 at 07:28, Gleb Popov <6yearold at gmail.com> wrote: > > def StoreStackF : InstRI<2, (outs), (ins IntRegs:$reg, i32imm:$i), > > "storestackf $reg, [$i]", [(store_stack i32:$reg, > AddrFI:$i)]>; > > >