llvm dev - Jan 2019 - Modern Vector Instructions: Compilation & Code Generation & Hardware Design @ LLVM Compiler Social Zurich - Thursday Jan 10

Dear all,

Thursday 10th Dec, 19:00, we discuss modern vectorization from compiler
representation, instruction set design, down to to hardware implementation. With
Simon Moll, Robin Kruppe, and Matheus Cavalcante we host experts from
Saarbruecken, Darmstadt and Zurich.

Talk 1: EVL -- Bringing LLVM's IR up to speed with vectorization.

There has been a recent surge in vector ISAs, let it be the RISC-V V extension,
ARM SVE or NEC SX-Aurora, all of which pose new demands to LLVM IR. Among their
novel features are an active vector length, full predication on all vector
instructions and a register length that is unknown at compile time. In this
talk, we present the Explicit Vector Length extension (EVL) for LLVM IR. EVL
provides primitives that are practical for both, backends and IR-level automatic
vectorizers. At the same time, EVL is compatible with LLVM-SVE and even existing
short SIMD ISAs stand to benefit from its consistent handling of predication.

Simon Moll is a fourth-year PhD student at Saarland University. He is best known
for his work on the Region Vectorizer (RV), which brings Outer-Loop and
Whole-Function Vectorization to LLVM IR with ISPC-like control-flow handling.

Talk 2: RISC-V Vectors in LLVM

The vector extension, called 'V' for short, adds standardized vector
processing capabilities to RISC-V. Similar to other modern vector architectures
such as Arm's Scalable Vector Extension (SVE), it supports a wide range of
processor designs by allowing the maximum size of a vector to be determined at
run time rather than being fixed at design time. These variable vector lengths,
and other features driven by the need to support many different applications and
microarchitectures, pose new challenges for compilers. This talk discusses some
of these challenges as well as the work happening in LLVM to address them, both
to support variable-length vectors in general as well as the particulars of
RISC-V vectors.

Robin Kruppe is an M.Sc. student at TU Darmstadt in the Embedded Systems and
Applications group. He is a member of the working group defining the RISC-V
vector extension and active in the LLVM community, leading the development of
LLVM support for that extension.

Talk 3: ARA: 64-bit RISC-V Vector Implementation in 22nm FDSOI

In this talk, we detail our experience in the design and implementation of the
RISC-V Vector Extensions (v0.4 draft) in an advanced silicon process. ARA is a
high-performance vector co-processor soft core that attaches to and cooperates
with an existing open-source RISC-V core Ariane, implementing RV64GC.

Matheus Cavalcante is a PhD Student at the Integrated Systems Laboratory of ETH
Zurich, under the supervision of Professor Luca Benini, working on HPC devices,
specifically vector processors.

# Registration

https://www.meetup.com/llvm-compiler-and-code-generation-socials-zurich/events/vxmqlqyzcbnb/

# What

A social meetup to discuss compilation and code generation questions with a
focus on LLVM, clang, Polly and related projects.

Our primary focus is to provide a venue (and drinks & snacks) that enables
free discussions between interested people without imposing an agenda/program.
This is a great opportunity to informally discuss your own projects, get project
ideas or just learn about what people at  ETH and around Zurich are doing with
LLVM.

Related technical presentations held by participants are welcome (please 
contact us).

# Who:  - Anybody interested -

  - ETH students and staff
  - LLVM developers and enthusiasts external to ETH

# When:  10.01.2018, 19:00

# Where: CAB E 72, ETH Zurich

# Earlier Socials

We have videos of earlier socials available at:
http://pollylabs.org/llvm-social-zurich.html

Best,
Tobias

> On 6 Jan 2019, at 4:52 pm, Tobias Grosser via llvm-dev <llvm-dev at
lists.llvm.org> wrote:
> 
> Dear all,
> 
> Thursday 10th Dec,
Wrong month ;)

On Sun, Jan 6, 2019, at 09:59, Nicholas Wilson wrote:
> 
> > On 6 Jan 2019, at 4:52 pm, Tobias Grosser via llvm-dev <llvm-dev at
lists.llvm.org> wrote:
> > 
> > Dear all,
> > 
> > Thursday 10th Dec,
> 
> Wrong month ;)
Thanks for letting me know. The date in the subject is fine though.

Best,
Tobias