search for: kruppe

...joerd.Meijer at arm.com> Cc: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Eli Friedman <efriedma at quicinc.com>; listmail at philipreames.com <listmail at philipreames.com>; llvm-dev <llvm-dev at lists.llvm.org>; Sander De Smalen <Sander.DeSmalen at arm.com>; hanna.kruppe at gmail.com <hanna.kruppe at gmail.com> Subject: Re: [llvm-dev] LV: predication Hi Sjoerd, On 5/18/20 3:43 PM, Sjoerd Meijer wrote: > You have similar problems with https://reviews.llvm.org/D79100 The new revision D79100<https://reviews.llvm.org/D79100> solves your comment 1), an...

...joerd.Meijer at arm.com> Cc: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Eli Friedman <efriedma at quicinc.com>; listmail at philipreames.com <listmail at philipreames.com>; llvm-dev <llvm-dev at lists.llvm.org>; Sander De Smalen <Sander.DeSmalen at arm.com>; hanna.kruppe at gmail.com <hanna.kruppe at gmail.com> Subject: Re: [llvm-dev] LV: predication On 5/19/20 12:38 PM, Sjoerd Meijer wrote: Hi Simon, Thanks for reposting the example, and looking at it more carefully, I think it is very similar to my first proposal. This was met with some resistance here be...

Hi Everyone, I am wondering how to use RISC-V V (Vector) extension instructions in LLVM IR. In 2019 Kruppe and Espasa gave a talk [1] overviewing the Vector extension and on slide 16 [2] they show LLVM IR samples which use the vector instructions through intrinsic functions, such as: %vl = call i32 @llvm.riscv.vsetvl(i32 %n) At the time of the talk (April 2019) LLVM support for the V extension was...

...joerd.Meijer at arm.com> Cc: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Eli Friedman <efriedma at quicinc.com>; listmail at philipreames.com <listmail at philipreames.com>; llvm-dev <llvm-dev at lists.llvm.org>; Sander De Smalen <Sander.DeSmalen at arm.com>; hanna.kruppe at gmail.com <hanna.kruppe at gmail.com> Subject: Re: [llvm-dev] LV: predication On 5/18/20 2:53 PM, Sjoerd Meijer wrote: Hi, I abandoned that approach and followed Eli's suggestion, see somewhere earlier in this thread, and emit an intrinsic that represents/calculates the active mask. I...

...joerd.Meijer at arm.com> Cc: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Eli Friedman <efriedma at quicinc.com>; listmail at philipreames.com <listmail at philipreames.com>; llvm-dev <llvm-dev at lists.llvm.org>; Sander De Smalen <Sander.DeSmalen at arm.com>; hanna.kruppe at gmail.com <hanna.kruppe at gmail.com> Subject: Re: [llvm-dev] LV: predication On 5/5/20 12:07 AM, Sjoerd Meijer via llvm-dev wrote: what we would like to generate is a vector loop with implicit predication, which works by setting up the the number of elements processed by the loop: hwloo...

...r code generating the V extension yet. The experimental-v support you see there is only MC-layer support, where you can use the V instructions in assembly (including inline assembly). There is currently (today) no way of turning LLVM IR vector intrinsics into RISC-V V extension instructions. Hanna Kruppe did have a fork of LLVM where she and others were working on prototype support for the V extension. The work on support for the V extension has continued, but not via upstreaming the exact changes in that prototype - instead there is an RFC about code generation support: http://lists.llvm.org/piper...

...te mask and VF parameters and why VF can’t be conservatively deduced from the mask/mask compute. From: Bruce Hoult [mailto:bruce at hoult.org] Sent: Thursday, January 31, 2019 5:13 PM To: Saito, Hideki <hideki.saito at intel.com> Cc: Philip Reames <listmail at philipreames.com>; Robin Kruppe <robin.kruppe at gmail.com>; David Greene <dag at cray.com>; via llvm-dev <llvm-dev at lists.llvm.org>; Maslov, Sergey V <sergey.v.maslov at intel.com>; Topper, Craig <craig.topper at intel.com> Subject: Re: [llvm-dev] [RFC] Vector Predication On Thu, Jan 31, 2019 at...

Hello, Now that I have my Samba4 DC running great on CentOS6.4 I was wondering if somebody could help understand better how to install and configure Samba4 with winbind and PAM. I used the tutorial here: [http://wiki.samba.org/index.php/Samba4/Winbind](http://wiki.samba.org/index.php/Samba4/Winbind) This got me through to the point where "Using pam_winbind" starts.

..., function call boundary, etc...) and a short sequence of vector ops Mask value from function call parameter is common. OpenMP declare simd function does exactly that for the masked cases. From: Philip Reames [mailto:listmail at philipreames.com] Sent: Thursday, January 31, 2019 4:05 PM To: Robin Kruppe <robin.kruppe at gmail.com> Cc: David Greene <dag at cray.com>; via llvm-dev <llvm-dev at lists.llvm.org>; Saito, Hideki <hideki.saito at intel.com>; Topper, Craig <craig.topper at intel.com>; Maslov, Sergey V <sergey.v.maslov at intel.com> Subject: Re: [llvm-dev...

On Tue, 7 Apr 2020 at 16:09, Renato Golin <rengolin at gmail.com> wrote: > > On Tue, 7 Apr 2020 at 12:51, Hanna Kruppe <hanna.kruppe at gmail.com> wrote: > > > 1. is LMUL always a multiple of ELEN? > > This happens to be true (at least in the current spec, disregarding > > some in-progress proposals) just because both are powers of two and > > the largest possible LMUL equals the sm...

On Wed, 2 Oct 2019 at 05:09, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote: > > My general feeling on this then is that both RVV and SV should avoid using > vscale. > > In the case of RVV, MVL is a hardware defined constant that is never > *intended* to be known by applications. There's no published detection > mechanism. Loops are supposed to be designed

...On Behalf Of Kai Wang via llvm-dev Sent: Tuesday, April 7, 2020 1:31 AM To: llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org> Cc: Roger Ferrer Ibanez <roger.ferrer at bsc.es<mailto:roger.ferrer at bsc.es>>; rengolin at gmail.co<mailto:rengolin at gmail.co>; robin.kruppe at gmail.com<mailto:robin.kruppe at gmail.com> Subject: [EXT] [llvm-dev] Questions about vscale Hi, In RISC-V v-extension, operations could operate on a group of vector registers; we called it LMUL. If LMUL equals 2, it means we could operate on 2 vector registers at the same time. So, w...

...Thanks, JinGu Kang ________________________________ From: Graham Hunter <Graham.Hunter at arm.com> Sent: 28 May 2019 10:46 To: JinGu Kang Cc: Joel Jones; Chris Lattner; Hal Finkel; Jones, Joel; dag at cray.com; Renato Golin; Kristof Beyls; Amara Emerson; Florian Hahn; Sander De Smalen; Robin Kruppe; llvm-dev at lists.llvm.org; mkuper at google.com; Sjoerd Meijer; Sam Parker; nd Subject: Re: [EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths Hi JinGu, > Above vectorized loop does not need tail loop. I guess we could map the %mask.vec to predicate register a...

...without a particular build flag. Also needs extra build bots. 3) Feature is always compiled and can be enabled regardless of LLVM build flags used. Option 2) has some precedent in the form of flags like `-fexperimental-new-pass-manager`. Option 3) doesn't have precedent in LLVM, but Robin Kruppe pointed out it has similarities to Rust, where experimental features can only be enabled in nightly builds. # Proposal Although we want to discourage downstream reliance on unratified extensions, there doesn't seem to be a strong motivation for requiring a custom LLVM build to force this. How...

...m-dev <llvm-dev-bounces at lists.llvm.org> on behalf of JinGu Kang via llvm-dev <llvm-dev at lists.llvm.org> Sent: 24 May 2019 21:47 To: Joel Jones; Chris Lattner; Hal Finkel; Jones, Joel; dag at cray.com; Renato Golin; Kristof Beyls; Amara Emerson; Florian Hahn; Sander De Smalen; Robin Kruppe; llvm-dev at lists.llvm.org; mkuper at google.com; Sjoerd Meijer; Sam Parker; Graham Hunter Cc: nd Subject: Re: [llvm-dev] [EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths Hi Joel, Thanks for your kind guide. > https://community.arm.com/developer/tools-softwa...

Thanks Daniel for the info. Siddharth On Thu, Sep 21, 2017 at 10:37 PM, Dániel Krupp <daniel.krupp at ericsson.com> wrote: > Hi Siddharth, > > > > since the CTU functionality is not yet part of the mainline clang (review > ongoing), you will need to clone our patched version of clang5 > > https://github.com/Ericsson/clang > > (ctu-clang5 branch) > > >

Hello, Not sure if this is the right forum for this question, but since I am running a Samba4 DC I thought I'd start here. I have create a separate OU to manage Groups and Users for Applications: 1) ou=myappX,ou=app,dc=mydomain,dc=home All Users (and other groups, e.g. Domain Users) are obviously found in : 2) cn=users,dc=mydomain,dc=home So I created a service

Hi, It has been a while that I did not come back to this topic, however I think I found a work-around for my initial problem. For information, what I was trying to do was: - Create an OU for a group of applications - Delegate control of this OU to a normal user (not helpdesk or domain admin) to be able to create groups and assign domain users to them The problem was, whenever I

On 31 July 2018 at 21:10, David A. Greene via llvm-dev <llvm-dev at lists.llvm.org> wrote: > Renato Golin via llvm-dev <llvm-dev at lists.llvm.org> writes: > >> Hi David, >> >> Let me put the last two comments up: >> >>> > But we're trying to represent slightly different techniques >>> > (predication, vscale change) which need

On Mon, 4 Feb 2019 at 22:04, Simon Moll <moll at cs.uni-saarland.de> wrote: > On 2/4/19 9:18 PM, Robin Kruppe wrote: > > > > On Mon, 4 Feb 2019 at 18:15, David Greene via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> Simon Moll <moll at cs.uni-saarland.de> writes: >> >> > You are referring to the sub-vector sizes, if i am understanding >> >...