Displaying 3 results from an estimated 3 matches for "22nm".
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2019 Jan 06
2
Modern Vector Instructions: Compilation & Code Generation & Hardware Design @ LLVM Compiler Social Zurich - Thursday Jan 10
...n M.Sc. student at TU Darmstadt in the Embedded Systems and Applications group. He is a member of the working group defining the RISC-V vector extension and active in the LLVM community, leading the development of LLVM support for that extension.
Talk 3: ARA: 64-bit RISC-V Vector Implementation in 22nm FDSOI
In this talk, we detail our experience in the design and implementation of the RISC-V Vector Extensions (v0.4 draft) in an advanced silicon process. ARA is a high-performance vector co-processor soft core that attaches to and cooperates with an existing open-source RISC-V core Ariane, implem...
2011 Aug 21
0
[LLVMdev] Xilinx zynq-7000 (7030) as a Gallium3D LLVM FPGA target
Luke Kenneth Casson Leighton wrote:
> On Sun, Aug 21, 2011 at 12:48 AM, Nick Lewycky<nicholas at mxc.ca> wrote:
>
>> The way in which Gallium3D targets LLVM, is that it waits until it receives
>> the shader program from the application, then compiles that down to LLVM IR.
>> That's too late to start synthesizing hardware (unless you're planning to
>>
2011 Aug 21
4
[LLVMdev] Xilinx zynq-7000 (7030) as a Gallium3D LLVM FPGA target
On Sun, Aug 21, 2011 at 12:48 AM, Nick Lewycky <nicholas at mxc.ca> wrote:
> The way in which Gallium3D targets LLVM, is that it waits until it receives
> the shader program from the application, then compiles that down to LLVM IR.
> That's too late to start synthesizing hardware (unless you're planning to
> ship an FPGA as the graphics card, in which case reprogramming