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2019 Jan 06
2
Modern Vector Instructions: Compilation & Code Generation & Hardware Design @ LLVM Compiler Social Zurich - Thursday Jan 10
...In this talk, we detail our experience in the design and implementation of the RISC-V Vector Extensions (v0.4 draft) in an advanced silicon process. ARA is a high-performance vector co-processor soft core that attaches to and cooperates with an existing open-source RISC-V core Ariane, implementing RV64GC. Matheus Cavalcante is a PhD Student at the Integrated Systems Laboratory of ETH Zurich, under the supervision of Professor Luca Benini, working on HPC devices, specifically vector processors. # Registration https://www.meetup.com/llvm-compiler-and-code-generation-socials-zurich/events/vxmqlqyzc...