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...c. student at TU Darmstadt in the Embedded Systems and Applications group. He is a member of the working group defining the RISC-V vector extension and active in the LLVM community, leading the development of LLVM support for that extension. Talk 3: ARA: 64-bit RISC-V Vector Implementation in 22nm FDSOI In this talk, we detail our experience in the design and implementation of the RISC-V Vector Extensions (v0.4 draft) in an advanced silicon process. ARA is a high-performance vector co-processor soft core that attaches to and cooperates with an existing open-source RISC-V core Ariane, implementing...