llvm dev - Feb 2017 - Add a custom intrinsic to the ARM backend

Hi,

I'm trying to add a new intrinsic to the ARM backend. The intrinsic should
a custom comparison.
To do so, I started with first defining the intrinsic in
llvm/include/llvm/IR/intrinsicsARM.td:

def int_foo_cmp : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
[]>;

The second step I did is adding a new pseudo instruction matching that
intrinsic in lib/Target/ARM/ARMInstInfo.td:

def FOO_CMP : PseudoInst<(outs GPR:$Rd), (ins GPR:$src1, GPR:$src2),
IIC_iCMPi,
                         [(set GPR:$Rd, (int_foo_cmp GPR:$src1,
GPR:$src2))]>;

Now I am a bit lost how to proceed. I want the instrinsic to do a certain
comparison chain and want to avoid any optimization on them.
Can someone guide me on how to proceed and emit machine instructions for
that intrinsic?

Thanks & Cheers
Max
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Hi Max,

On 10 February 2017 at 02:12, Max Muster via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> Can someone guide me on how to proceed and emit machine instructions for
> that intrinsic?
Next step is probably to handle FOO_CMP in ARMExpandPseudoInsts.cpp.
It's a pass that runs after most optimizations (maybe even all) so
it's where most sensitive pseudo-instructions are expanded.

There's plenty of other examples of how to do it in that file (the
ExpandMI function), all following pretty similar patterns.

Cheers.

Tim.

Hi Tim,

Thank you for your response. Meanwhile, I stumbled over the same function.
I added a case in ExpandMI for ARM::FOO_CMP.

First, I want to emit a simple equal comparison for that intrinsic.
However, I don't understand how to retrieve the return register for the
intrinsic.
I tried the following:

case ARM::FOO: {
      DebugLoc DL = MBBI->getDebugLoc();

      BuildMI(&MBB, DL, TII->get(ARM::CMPrr))
        .addReg(MI.getOperand(1).getReg())
        .addReg(MI.getOperand(2).getReg())
        .addImm(ARMCC::NE);

      MI.eraseFromParent(); // The pseudo is gone now.
      return true;
    }

AFAIK, BuildMI() expects another parameter for the destination but how to
retrieve that from the pseudo instruction?
In the future, the implementation of this instruction will get more complex
and requires a temporary register for computation. How can I allocate a
register at that stage of compiling?

Thanks & Cheers,
Max

On Fri, Feb 10, 2017 at 3:30 PM, Tim Northover <t.p.northover at
gmail.com>
wrote:
> Hi Max,
>
> On 10 February 2017 at 02:12, Max Muster via llvm-dev
> <llvm-dev at lists.llvm.org> wrote:
> > Can someone guide me on how to proceed and emit machine instructions
for
> > that intrinsic?
>
> Next step is probably to handle FOO_CMP in ARMExpandPseudoInsts.cpp.
> It's a pass that runs after most optimizations (maybe even all) so
> it's where most sensitive pseudo-instructions are expanded.
>
> There's plenty of other examples of how to do it in that file (the
> ExpandMI function), all following pretty similar patterns.
>
> Cheers.
>
> Tim.
>
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