similar to: Add a custom intrinsic to the ARM backend

Displaying 20 results from an estimated 200 matches similar to: "Add a custom intrinsic to the ARM backend"

2015 Mar 09
2
[LLVMdev] LLVM Backend DAGToDAGISel INTRINSIC
I am currently working on DAGToDAGISel class for MIPS and am trying to figure out a way to use INTRINSIC_W_CHAIN for an intrinsic which can return a value. My intrinsic is defined as: Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],[IntrReadWriteArgMem]>; i.e. it has four arguments and one return value In DAGToDAGISel when I try to pass it with four arguments and
2008 May 07
0
[LLVMdev] Creation of Intrinsics with Pointer Return Types
Hello, LLVM's intrinsic overloading mechanism does not currently support overloading on pointer types. Patches to implement this would be welcome. Dan On May 7, 2008, at 9:25 AM, aditya vishnubhotla wrote: > Hi, > I tried creating intrinsics which are to be > placeholders for a set of instructions (actually a section of a > basic block) to be executed elsewhere(for e.g. in
2008 May 07
2
[LLVMdev] Creation of Intrinsics with Pointer Return Types
<table cellspacing='0' cellpadding='0' border='0' ><tr><td style='font: inherit;'>Hi,<br>I tried creating intrinsics which are to be<br>placeholders for a set of instructions (actually a section of a basic block) to be executed elsewhere(for e.g. in HW).<br>These intrinsics are to take care of the data dependencies of the set of
2017 Jul 07
2
Lowering Select to Two Predicated Movs
My bad for not looking further. I'm still somewhat confused though. MOVCCr gets expanded in the ARMExpandPseudoInsts pass, and it still seems only a case of one instruction replacing the other. My worry of emitting two instructions, is that a dead code pass will eliminate the first instruction cause it thinks the second instruction is defining the same register. -Dilan On Fri, Jul 7, 2017
2018 Jan 16
2
Why do backend pass definitions call a seperate function just to call the constructor?
Things like this in `lib/Target/ARM/ARMExpandPseudoInsts.cpp` FunctionPass *llvm::createARMExpandPseudoPass() { > return new ARMExpandPseudo(); > } And other functions have basically the same style. What's the point of doing it this way instead of just calling `new ARMExpandPseudo` in any place that you would have called this function? -- Ahmed Samara M.S. Computer Engineering
2015 Dec 01
2
LICM doesn't work for IntrReadMem intrinsic function
Hi, All, Suppose I define one memory read only intrinsic function "foo" in Intrinsics.td like this def int_foo : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrReadMem]>; Suppose I have the following IR, which means the intrinsic function "foo" is called 10 times in a loop. Since the parameters of function "foo" are invariant and the function
2012 Jan 20
2
[LLVMdev] Tablegen: How to define a Pattern with multiple result instructions
Hi, I'm trying to create a Pattern that looks something like this: def my_inst : Instruction < let OutOperandList = (outs REG:$dst); let InOperandList = (ins imm:$src); let Uses = [R0]; > def int_my_intrinsic : Intrinsic < [llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [] >; def : Pattern < (int_my_intrinsic imm:$a, imm:$b, imm:$c), [(set R0, (MOV_IMM
2014 Apr 06
2
[LLVMdev] Instruction dependency in ARM backend
Hi I'm working on a POC adding Windows Phone (ARM) support to the ARM backend. I've encountered the following problem. Microsoft's COFF linker/loader supports a single relocation type ( IMAGE_REL_ARM_MOV32T) on continuous movw/movt Thumb2 instructions opposed to ELF and Mach-O which support relocation per instruction (one for movw and movt). I need to make sure that in case of
2015 Dec 01
2
LICM doesn't work for IntrReadMem intrinsic function
Thanks for your reply, escha, Yes, -loop-rorate makes it work. Regards, Xiangyang 2015-12-01 12:48 GMT-05:00 <escha at apple.com>: > > > On Dec 1, 2015, at 9:30 AM, Xiangyang Guo via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > Hi, All, > > > > Suppose I define one memory read only intrinsic function "foo" in >
2018 Nov 07
2
how to add a instruction
Hi,every one. I' in trouble again. I want add a new intrinsic mapping a new instruction. I add the int_x86_max_qb as fllowing: def int_x86_max_qb: GCCBuiltin<"__builtin_x86_max_qb">, Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [Commutative]>; BUILTIN(__builtin_x86_max_qb, "iii", "") I define the intrinsic as Pseudo instruction,it
2012 Jul 16
3
[LLVMdev] RFC: LLVM incubation, or requirements for committing new backends
Tom, I think it might be productive to fork this thread to discuss making the requirements for upstreaming a new LLVM target more explicit and open. I'd also like to gauge interest in an idea I've discussed privately with a few community members, namely the concept of having a semi-official "incubation" system whereby proposed backends could get a trial run before becoming part
2011 May 26
0
[LLVMdev] x86 SSE4.2 CRC32 intrinsics renamed
FYI, The CRC64 intrinsics were renamed to CRC32 since there is no such thing. See below for details. Chad On May 26, 2011, at 4:13 PM, Chad Rosier wrote: > Author: mcrosier > Date: Thu May 26 18:13:19 2011 > New Revision: 132163 > > URL: http://llvm.org/viewvc/llvm-project?rev=132163&view=rev > Log: > Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist.
2018 Sep 17
2
error about adding an trinsics
Hi,every one. This problem has been bothering me for several days.I really hope that you can help me. I want to add an trinsics in X86. This trinsics can compare two numbers and return the larger. There are the changes I do as fllowing. In /tools/clang/include/clang/Basic/BuiltinsX86.def : BUILTIN(__builtin_x86_max_qb, "iii", "") In include/llvm/IR/IntrinsicsX86.td : let
2018 Sep 06
2
Adding an trinsics in x86
Hi Everyone! I am a newbie at llvm. So the question may be fundamental but difficult to me. I want to add an trinsics in x86 and make the following changes.I want that max_qb can find the max of two Integers and return it. In src/include/llvm/IR/Intrinsics.td : let TargetPrefix = "x86" in { def int_x86_max_qb: GCCBuiltin<"__builtin_x86_max_qb">,
2015 Oct 22
2
add intrinsic function support for customized backend
Hi, Gaël, Thanks for your detailed reply. I tried the pattern matching first, however, the intrinsic function is matching with a normal function call. For example, I have the following IR, which contains intrinsic function "foo": ***************************************************************************************** *define i32 @test_func() {* *EntryBlock:* * %0 = call i32
2010 May 27
1
[LLVMdev] builtin naming
Hi Sorry ...I know I should be mailing to the clang list but I am waiting for my subscription. My question is on how to name my builtin in source if i have a intrinsic definition like def int_mytarget_get_id : : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>; I tried __builtin_mytarget_get_id and clang still didnt generate my intrinsic. thanks shrey
2016 Mar 21
1
define intrinsic function with pointer-typed parameter
Hi, If I define a intrinsic function with pointer-typed parameter, for example, def llvm_foo_ptr_ty : LLVMPointerType<llvm_i16_ty>; def int_foo_get : Intrinsic<[llvm_foo_ptr_ty], [llvm_foo_ptr_ty, llvm_i32_ty], [IntrReadArgMem]>; How to lower it for the backend? I'm not sure what kind of register (i16 or i32 or i32) is needed in this case? If the parameter is
2015 Oct 22
2
add intrinsic function support for customized backend
Hi, All, I want to add one intrinsic function for my particular backend. Let's say the intrinsic function is named "foo" which takes two i32 inputs and has one i32 output. First, I add this line "def int_foo : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrReadArgMem]>;" in /include/llvm/IR/Intrinsics.td. Then, in my target/InstrInfo.td, I'm supposed
2009 Jun 24
3
[LLVMdev] Replacing instruction in LLVM IR by an intrinsics
Hi everyone, I am trying to write a pass, that finds some instructions and replaces them with my intrinsics, but I am having problem understanding, how this should be done. Let's say I have this instruction: %tmp14 = load i32* getelementptr ([32 x i32]* @gpregs, i32 0, i64 28) and i need to read the load's operands and replace it by let's say: %tmp14 = call i32
2011 Jun 17
0
[LLVMdev] RFC: Integer saturation intrinsics
On Fri, Jun 17, 2011 at 3:08 PM, Evan Cheng <evan.cheng at apple.com> wrote: > Hi all, > > I'm proposing integer saturation intrinsics. > > def int_ssat : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, llvm_i32_ty]>; > def int_usat : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, llvm_i32_ty]>; > > The first operand is the integer value