search for: armexpandpseudoinsts

My bad for not looking further. I'm still somewhat confused though. MOVCCr gets expanded in the ARMExpandPseudoInsts pass, and it still seems only a case of one instruction replacing the other. My worry of emitting two instructions, is that a dead code pass will eliminate the first instruction cause it thinks the second instruction is defining the same register. -Dilan On Fri, Jul 7, 2017 at 11:20 AM Friedman,...

Things like this in `lib/Target/ARM/ARMExpandPseudoInsts.cpp` FunctionPass *llvm::createARMExpandPseudoPass() { > return new ARMExpandPseudo(); > } And other functions have basically the same style. What's the point of doing it this way instead of just calling `new ARMExpandPseudo` in any place that you would have called this function? -...

Hi I'm working on a POC adding Windows Phone (ARM) support to the ARM backend. I've encountered the following problem. Microsoft's COFF linker/loader supports a single relocation type ( IMAGE_REL_ARM_MOV32T) on continuous movw/movt Thumb2 instructions opposed to ELF and Mach-O which support relocation per instruction (one for movw and movt). I need to make sure that in case of

On 16 January 2018 at 20:40, Ahmed Samara via llvm-dev <llvm-dev at lists.llvm.org> wrote: > Things like this in `lib/Target/ARM/ARMExpandPseudoInsts.cpp` > >> FunctionPass *llvm::createARMExpandPseudoPass() { >> return new ARMExpandPseudo(); >> } > > And other functions have basically the same style. > > What's the point of doing it this way instead of just calling `new > ARMExpandPseudo` in any place t...

Hi, I'm trying to add a new intrinsic to the ARM backend. The intrinsic should a custom comparison. To do so, I started with first defining the intrinsic in llvm/include/llvm/IR/intrinsicsARM.td: def int_foo_cmp : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; The second step I did is adding a new pseudo instruction matching that intrinsic in lib/Target/ARM/ARMInstInfo.td:

...e hoisted without the other, and MachineLICM is not aggressive enough to recognize chains of dependent, loop-invariant cheap instructions. At the time, the advice was to implement a PseudoInstruction for lui+ori and lower it in a C++ pass, as is done in ARM (see MOVi32imm in ARMInstrInfo.td and ARMExpandPseudoInsts.cpp). I did this for my target and it worked fine, so MIPS could do the same. To me, that solution isn't too satisfying because you have to do this for every multi-instruction TableGen pattern to get them hoisted out of loops, but the philosophy seems to be to keep MachineLICM simple. -Matt...

Hi, I was wondering what would be the best way to lower a select operation two predicated movs. I looked through the ARM, MIPS, and NVPTX backends and they all seem to lower a select to some sort of conditional move or native select operation. Ex. select t3, cond, t2, t1 Becomes cond mov t3, t2 !cond mov t3, t1 -Dilan -------------- next part -------------- An HTML attachment was scrubbed...

...machine dead code elimination? -Dilan On Fri, Jul 7, 2017 at 12:37 PM Friedman, Eli <efriedma at codeaurora.org> wrote: > On 7/7/2017 12:10 PM, Dilan Manatunga wrote: > > My bad for not looking further. I'm still somewhat confused though. > > MOVCCr gets expanded in the ARMExpandPseudoInsts pass, and it still > > seems only a case of one instruction replacing the other. > > The output of MOVCCr is tied to the "false" input using RegConstraint. > The register allocator puts the "false" value into the destination > register, then MOVCCr gets expande...

...mStackSlot when the instruction loads the whole stack slot. That is, the offset is zero, and the stack slot size matches the register size. If you need the rewriter to be able to undo a stack slot load/store, you will have to create pseudo-instructions for accumulator loads and stores. Compare the ARMExpandPseudoInsts pass. We are working towards a design where we don't need these rewriter shenanigans. In fact, the trivial rewriter will be used instead. -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/pkcs7-signature Size: 1929 bytes Desc: not...

On Apr 24, 2012, at 11:48 PM, Fan Dawei wrote: > For the following code fragment, > > ; <label>:27 ; preds = %27, %entry > %28 = load volatile i32* inttoptr (i64 2149581832 to i32*), align 8 > %29 = icmp slt i32 %28, 0 > br i1 %29, label %27, label %loop.exit > > loop.exit: ; preds = %27

On Tuesday, July 20, 2010 4:04 PM, Jakob Stoklund Olesen > > On Jul 20, 2010, at 10:57 AM, Ken Dyck wrote: > > > Does anybody have any tips for generating spills/reloads for large > > non-vector registers? > > [snip] > > > This is quite simple to handle. A register > MachineOperand has a subreg field for this > purpose. It is used to pick out subregisters

For the following code fragment, ; <label>:27 ; preds = %27, %entry %28 = load volatile i32* inttoptr (i64 2149581832 to i32*), align 8 %29 = icmp slt i32 %28, 0 br i1 %29, label %27, label %loop.exit loop.exit: ; preds = %27 llc will generate following MIPS code, $BB0_1: lui $3, 32800 ori $3, $3, 1032 lw