llvm dev - Mar 2011 - [LLVMdev] Possible missed optimization?

Hello, I've noticed the following issue while testing some codegen tests, i
would like to know if it's a missed optimization or i missed something out
here. This is for an out of tree backend im writing. I managed to reduce it
to the following C function:

void foo(int *a) // int here is 16bits
{
  *a &= 0xFF;
}

This is the code before regalloc:
    Live Ins: %R25R24
    %vreg0<def> = COPY %R25R24; DREGS:%vreg0
    %vreg2<def> = COPY %vreg0; PTRREGS:%vreg2 DREGS:%vreg0
    %vreg1<def> = LDWRd %vreg2;
mem:LD2[%a](align=1)(tbaa=!"int")
DLDREGS:%vreg1 PTRREGS:%vreg2
    %vreg3<def> = ANDIWRdK %vreg1, 255; DLDREGS:%vreg3,%vreg1
    %vreg5<def> = COPY %vreg0; PTRREGS:%vreg5 DREGS:%vreg0
    STWRr %vreg5, %vreg3<kill>;
mem:ST2[%a](align=1)(tbaa=!"int")
PTRREGS:%vreg5 DLDREGS:%vreg3
    RET
>From above, the 3rd COPY instruction is redundant since it does exactly the
same thing as the second COPY instruction, so the stw (store) instr should
take %vreg2 instead of %vreg5. After regalloc we get this code:
    Live Ins: %R25R24
    %R27R26<def> = COPY %R25R24
    %R19R18<def> = LDWRd %R27R26<kill>;
mem:LD2[%a](align=1)(tbaa=!"int") //
<---------- why is R27:R26 killed?
    %R19R18<def> = ANDIWRdK %R19R18, 255
    %R27R26<def> = COPY %R25R24<kill> // <------------------ why
is this
emitted?
    STWRr %R27R26<kill>, %R19R18<kill>;
mem:ST2[%a](align=1)(tbaa=!"int")
    RET

The last copy instruction should be removed as pointed out above, but since
R27R26 is killed in the load instruction it has to be emitted. About the
insane amount of regclasses there, the load/store and the andi instructions
take subsets of regs from the main register class, they cant work with all
registers, that's why STW and LDW needs R27R26 since it belongs to the ptr
reg class and not R25R24 where the "a" ptr is. As a test i made the
load/store instructions work with the DREGS which is the main class and the
problem was solved, but of course this is illegal code :)

Thanks
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On Mar 24, 2011, at 5:42 PM, Borja Ferrer wrote:
> The last copy instruction should be removed as pointed out above, but since
R27R26 is killed in the load instruction it has to be emitted. About the insane
amount of regclasses there, the load/store and the andi instructions take
subsets of regs from the main register class, they cant work with all registers,
that's why STW and LDW needs R27R26 since it belongs to the ptr reg class
and not R25R24 where the "a" ptr is. As a test i made the load/store
instructions work with the DREGS which is the main class and the problem was
solved, but of course this is illegal code :)
The coalescer cannot join copies with disjoint register classes.

You need to make sure that there is a register class representing the
intersection. Currently, such register classes cannot be inferred automatically
by TableGen.

/jakob

Hello Jakob, thanks for the reply. The three regclasses involved here are
all subsets from each other and aren't disjoint. These are the basic
descriptions of the regclasses involved to show what i mean:

DREGS: R31R30, R29R28 down to R1R0         (16 regs)
DLDREGS: R31R30, R29R28 down to R17R16  (8 regs)
PTRREGS: R31R30, R29R28, R27R26             (3 regs)

All classes intersect each other giving as a result the smaller class:
DREGSxDLDREGS=DLDREGS / DLDREGSxPTRREGS=PTRREGS, etc. That's why i think the
coalescer should work since the regclasses overlap completely.
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