search for: vreg6

...updated: 96L %vreg8<def> = COPY %R25R24<kill>; PTRREGS:%vreg8 updated: 32L %vreg5<def> = COPY %R25R24; PTRREGS:%vreg5 Joined. Result = %R25R24,inf = [0L,96d:0) 0 at 0L-phidef 32L %vreg5<def> = COPY %R25R24; PTRREGS:%vreg5 Not coalescable. 64L %vreg6<def> = COPY %vreg4<kill>; DLDREGS:%vreg6,%vreg4 Considering merging %vreg4 with %vreg6 to DLDREGS RHS = %vreg4 = [48d,64d:0) 0 at 48d LHS = %vreg6 = [64d,80d:1)[80d,112d:0) 0 at 80d 1 at 64d updated: 48L %vreg6<def> = LDWRd %vreg5<kill>; mem:...

...<def> = COPY %R25R24<kill>; PTRREGS:%vreg8 > updated: 32L %vreg5<def> = COPY %R25R24; PTRREGS:%vreg5 > Joined. Result = %R25R24,inf = [0L,96d:0) 0 at 0L-phidef > 32L %vreg5<def> = COPY %R25R24; PTRREGS:%vreg5 > Not coalescable. > 64L %vreg6<def> = COPY %vreg4<kill>; DLDREGS:%vreg6,%vreg4 > Considering merging %vreg4 with %vreg6 to DLDREGS > RHS = %vreg4 = [48d,64d:0) 0 at 48d > LHS = %vreg6 = [64d,80d:1)[80d,112d:0) 0 at 80d 1 at 64d > updated: 48L %vreg6<def> = LDWRd %vre...

Hi, I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : // BEFORE LOOP ... Some COPYs.... 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2 416B%vreg48<def> = COPY %vreg3<kill>; R600_Reg128:%vreg48,%vreg3 432B%vreg49<def> = COPY %vreg13<kill&gt...

On Mar 26, 2011, at 1:04 PM, Borja Ferrer wrote: > Hello Jakob, thanks for the reply. The three regclasses involved here are all subsets from each other and aren't disjoint. These are the basic descriptions of the regclasses involved to show what i mean: > > DREGS: R31R30, R29R28 down to R1R0 (16 regs) > DLDREGS: R31R30, R29R28 down to R17R16 (8 regs) > PTRREGS:

...i Vincent, On 24/10/2012 23:26, Vincent Lejeune wrote: > Hi, > > I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. > > The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : > > // BEFORE LOOP > ... Some COPYs.... > 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2 > 416B%vreg48<def> = COPY %vreg3<kill>; R600_Reg128:%vreg48,%vreg3 > 432B%vreg49<def&...

Hello Jakob, thanks for the reply. The three regclasses involved here are all subsets from each other and aren't disjoint. These are the basic descriptions of the regclasses involved to show what i mean: DREGS: R31R30, R29R28 down to R1R0 (16 regs) DLDREGS: R31R30, R29R28 down to R17R16 (8 regs) PTRREGS: R31R30, R29R28, R27R26 (3 regs) All classes intersect each other

...,%vreg14 456B %vreg18<def> = DIVD %vreg16, %vreg17; G8RC:%vreg18,%vreg16,%vreg17 464B %vreg21<def> = DIVD %vreg19, %vreg20; G8RC:%vreg21,%vreg19,%vreg20 472B %vreg5<def> = ADDIStocHA %X2, <ga:@A>; G8RC_and_G8RC_NOX0:%vreg5 480B %vreg6<def> = LDtocL <ga:@A>, %vreg5, %X2<imp-use>; mem:LD8[GOT] G8RC_and_G8RC_NOX0:%vreg6,%vreg5 504B %X3<def> = LI8 0 512B STD %vreg4, 0, %vreg6; mem:ST8[getelementptr inbounds ([100 x i64], [100 x i64]* @A, i64 0, i64 0)](tbaa=!4) G8RC:%vreg4 G8RC_and_G8...

...reg3; GR64:%vreg3 CALL64pcrel32 <ga:@puts>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSP<imp-def>, %EAX<imp-def> ADJCALLSTACKUP64 0, 0, %RSP<imp-def,dead>, %EFLAGS<imp-def,dead>, %RSP<imp-use> %vreg4<def> = COPY %EAX; GR32:%vreg4 MOV64rr %vreg6, %RSP; GR64:%vreg6 Successors according to CFG: BB#1 BB#1: derived from LLVM BB %entry Predecessors according to CFG: BB#0 BB#2 CMP64rr %vreg6, %RBP, %EFLAGS<imp-def>; GR64:%vreg6 JE_4 <BB#3>, %EFLAGS<imp-use> Successors according to CFG: BB#3 BB#2 BB#2: derived from LLVM BB %entr...

...%vreg4,%vreg3 > %vreg1<def> = PHI %vreg5, <BB#0>, %vreg2, <BB#1>; IntRegs:%vreg1,%vreg5,%vreg2 > %vreg2<def> = LDriw %vreg0<kill>, 0; mem:LD4[%stack.0.in] IntRegs:%vreg2,%vreg0 > %vreg3<def> = ADD_ri %vreg2, 8; IntRegs:%vreg3,%vreg2 > %vreg6<def> = CMPEQri %vreg2, 0; PredRegs:%vreg6 IntRegs:%vreg2 > JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6 > JMP <BB#2> > Successors according to CFG: BB#2 BB#1 > > BB#2: derived from LLVM BB %for.end > Predecessors acco...

...%vreg10<kill>; IntRegs:%vreg1,%vreg10 <<<<<<<<<<<<< First use uninitialized vreg10 %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in] IntRegs:%vreg10,%vreg9 %vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10 %vreg6<def> = CMPEQri %vreg10, 0; PredRegs:%vreg6 IntRegs:%vreg10 JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6 JMP <BB#2> Successors according to CFG: BB#2 BB#1 BB#2: derived from LLVM BB %for.end Predecessors according to CFG: BB#1...

..., %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%vreg3 FPUaOffsetClass:%vreg0,%vreg2 64B %vreg4<def> = COPY %vreg3; FPUaOffsetClass:%vreg4 FPUaROUTMULRegisterClass:%vreg3 80B %vreg5<def> = MOVSUTO_A_iSLo 1056964608; FPUaOffsetClass:%vreg5 96B %vreg6<def> = FMUL_A_oo %vreg0, %vreg5, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%vreg6 FPUaOffsetClass:%vreg0,%vreg5 112B %vreg7<def> = COPY %vreg6; FPUaOffsetClass:%vreg7 FPUaROUTMULRegisterClass:%vreg6 128B %vreg8<def> = FADD_A_oo %vreg4, %vreg7, %RF...

...ill>; IntRegs:%vreg1,%vreg10 <<<<<<<<<<<<< First use uninitialized vreg10 > %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in] IntRegs:%vreg10,%vreg9 > %vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10 > %vreg6<def> = CMPEQri %vreg10, 0; PredRegs:%vreg6 IntRegs:%vreg10 > JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6 > JMP <BB#2> > Successors according to CFG: BB#2 BB#1 > > BB#2: derived from LLVM BB %for.end > Predecessors ac...

...lt;def> = COPY %T1_Y; R600_TReg32:%vreg2 %vreg1<def> = COPY %T1_Z; R600_TReg32:%vreg1 %vreg0<def> = COPY %T1_W; R600_TReg32:%vreg0 RESERVE_REG 0 %vreg4<def> = FNEG_R600 %vreg3; R600_Reg32:%vreg4 R600_TReg32:%vreg3 %vreg5<def> = MOV_IMM_F32 0.000000e+00; R600_Reg32:%vreg5 %vreg6<def> = ADD 0, 0, 1, 0, 0, 0, %vreg4<kill>, 0, 0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg6,%vreg4,%vreg5 %vreg7<def> = FNEG_R600 %vreg2; R600_Reg32:%vreg7 R600_TReg32:%vreg2 %vreg8<def> = ADD 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, %vreg5, 0, 0,...

...edge ], [ 0, %entry ] ret i32 %sum.0.lcssa } The emitted blocks are: Function Live Ins: %R0 in %vreg2 BB#0: derived from LLVM BB %entry Live Ins: %R0 %vreg2<def> = COPY %R0; IntRegs:%vreg2 %vreg3<def> = MV 0; SRegs:%vreg3 CMP %vreg2, 1, %FLAG<imp-def>; IntRegs:%vreg2 %vreg6<def> = COPY %vreg3; SRegs:%vreg6,%vreg3 BR_cc <BB#2>, 20, %FLAG<imp-use,kill> BR <BB#1> Successors according to CFG: BB#1(20) BB#2(12) BB#1: derived from LLVM BB %for.cond.for.end_crit_edge Predecessors according to CFG: BB#0 %vreg4<def> = MV %vreg4; IntReg...

...IntRegs:%vreg0,%vreg4,%vreg3 %vreg1<def> = PHI %vreg5, <BB#0>, %vreg2, <BB#1>; IntRegs:%vreg1,%vreg5,%vreg2 %vreg2<def> = LDriw %vreg0<kill>, 0; mem:LD4[%stack.0.in] IntRegs:%vreg2,%vreg0 %vreg3<def> = ADD_ri %vreg2, 8; IntRegs:%vreg3,%vreg2 %vreg6<def> = CMPEQri %vreg2, 0; PredRegs:%vreg6 IntRegs:%vreg2 JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6 JMP <BB#2> Successors according to CFG: BB#2 BB#1 BB#2: derived from LLVM BB %for.end Predecessors according to CFG: BB#1...

Hi, I'm having some trouble wirting an instruction in the X86 backend. I made a new intrinsic and I wrote a custom inserter for my intrinsic in the X86 backend. Everything works fine, except for one instruction that I can't find how to write. I want to add this instruction in one of my machine basic block: mov [rdi], 0 How can I achieve that with the LLVM api? I tried several

...during if-conversion? Apart from that, I have no clue... Here is the end of a log I get under gdb (gdb used for getting a more informative backtrace): # *** IR Dump Before Calculate spill weights ***: # Machine code for function CGA_kernel_read: Post SSA Function Live Ins: %P0 in %vreg5, %P1 in %vreg6 Function Live Outs: %P15 0B BB#0: derived from LLVM BB %entry Live Ins: %P0 %P1 16B %vreg6<def> = COPY %P1; IntRegs:%vreg6 48B %vreg8<def> = MOV32ri <ga:@fifo>, pred:%noreg; IntRegs:%vreg8 dbg:../src/getbits.c:46:1 64B %vreg9<def> = LDUBri %vreg8, 1, pred:%noreg; me...

On Jun 13, 2012, at 10:49 AM, Sergei Larin <slarin at codeaurora.org> wrote: > So if this early exit is taken: > > // SSA defs do not have output/anti dependencies. > // The current operand is a def, so we have at least one. > if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) > return; > > we do not ever get to this point: > >

...e: >> Function Live Ins: %R0 in %vreg2 >> >> BB#0: derived from LLVM BB %entry >> Live Ins: %R0 >> %vreg2<def> = COPY %R0; IntRegs:%vreg2 >> %vreg3<def> = MV 0; SRegs:%vreg3 >> CMP %vreg2, 1, %FLAG<imp-def>; IntRegs:%vreg2 >> %vreg6<def> = COPY %vreg3; SRegs:%vreg6,%vreg3 >> BR_cc <BB#2>, 20, %FLAG<imp-use,kill> >> BR <BB#1> >> Successors according to CFG: BB#1(20) BB#2(12) >> >> BB#1: derived from LLVM BB %for.cond.for.end_crit_edge >> Predecessors according t...

...0; mem:LD4[@b] GR:%vreg1,%vreg0 %vreg2<def> = MOVIMM21 0; GR:%vreg2 %vreg3<def> = CMPGT %vreg1<kill>, %vreg2; PR:%vreg3 GR:%vreg1,%vreg2 %vreg4<def> = MOVIMM21 8; GR:%vreg4 %vreg5<def> = MOV %vreg4<kill>; GR:%vreg5,%vreg4 %vreg6<def> = MOVIMM21 23; GR:%vreg6 %vreg7<def,tied1> = CMOV %vreg5<tied0>, %vreg6<kill>, %vreg3<kill>; GR:%vreg7,%vreg5,%vreg6 PR:%vreg3 %vreg8<def> = MOVL_GA <ga:@a>; GR:%vreg8 STHri %vreg8<kill>, 0, %vreg7<kill>; mem:ST4[@a]...