Displaying 20 results from an estimated 33 matches for "vreg8".
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2011 Mar 26
2
[LLVMdev] Possible missed optimization?
...ion: foo
********** JOINING INTERVALS ***********
entry:
16L %vreg0<def> = COPY %R25R24<kill>; DREGS:%vreg0
Considering merging %vreg0 with physreg %R25R24
RHS = %vreg0 = [16d,96d:0) 0 at 16d
LHS = %R25R24,inf = [0L,16d:0) 0 at 0L-phidef
updated: 96L %vreg8<def> = COPY %R25R24<kill>; PTRREGS:%vreg8
updated: 32L %vreg5<def> = COPY %R25R24; PTRREGS:%vreg5
Joined. Result = %R25R24,inf = [0L,96d:0) 0 at 0L-phidef
32L %vreg5<def> = COPY %R25R24; PTRREGS:%vreg5
Not coalescable.
64L %vreg6<def> = COPY %...
2018 Apr 23
2
pre-RA scheduling/live register analysis optimization (handle move) forcing spill of registers
...8; FPUaOffsetClass:%vreg5
96B %vreg6<def> = FMUL_A_oo %vreg0, %vreg5, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%vreg6 FPUaOffsetClass:%vreg0,%vreg5
112B %vreg7<def> = COPY %vreg6; FPUaOffsetClass:%vreg7 FPUaROUTMULRegisterClass:%vreg6
128B %vreg8<def> = FADD_A_oo %vreg4, %vreg7, %RFLAGA<imp-def,dead>; FPUaROUTADDRegisterClass:%vreg8 FPUaOffsetClass:%vreg4,%vreg7
144B %FA_ROFF0<def> = COPY %vreg8; FPUaROUTADDRegisterClass:%vreg8
176B MOVSUTO_SU_os_rpc %SU_ROFF0<kill>, %RPC<imp-def,dead>
192...
2011 Mar 28
0
[LLVMdev] Possible missed optimization?
...TERVALS ***********
> entry:
> 16L %vreg0<def> = COPY %R25R24<kill>; DREGS:%vreg0
> Considering merging %vreg0 with physreg %R25R24
> RHS = %vreg0 = [16d,96d:0) 0 at 16d
> LHS = %R25R24,inf = [0L,16d:0) 0 at 0L-phidef
> updated: 96L %vreg8<def> = COPY %R25R24<kill>; PTRREGS:%vreg8
> updated: 32L %vreg5<def> = COPY %R25R24; PTRREGS:%vreg5
> Joined. Result = %R25R24,inf = [0L,96d:0) 0 at 0L-phidef
> 32L %vreg5<def> = COPY %R25R24; PTRREGS:%vreg5
> Not coalescable.
> 64L %...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...TReg32:%vreg3
%vreg5<def> = MOV_IMM_F32 0.000000e+00; R600_Reg32:%vreg5
%vreg6<def> = ADD 0, 0, 1, 0, 0, 0, %vreg4<kill>, 0, 0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg6,%vreg4,%vreg5
%vreg7<def> = FNEG_R600 %vreg2; R600_Reg32:%vreg7 R600_TReg32:%vreg2
%vreg8<def> = ADD 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg8,%vreg7,%vreg5
%vreg10<def> = IMPLICIT_DEF; R600_Reg128:%vreg10
%vreg9<def,tied1> = INSERT_SUBREG %vreg10<tied0>, %vreg6<kill>, sel_x; R600_Reg128:%vre...
2011 Mar 26
0
[LLVMdev] Possible missed optimization?
On Mar 26, 2011, at 1:04 PM, Borja Ferrer wrote:
> Hello Jakob, thanks for the reply. The three regclasses involved here are all subsets from each other and aren't disjoint. These are the basic descriptions of the regclasses involved to show what i mean:
>
> DREGS: R31R30, R29R28 down to R1R0 (16 regs)
> DLDREGS: R31R30, R29R28 down to R17R16 (8 regs)
> PTRREGS:
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
...edecessors according to CFG: BB#1
> %vreg7<def> = LDriw %vreg1<kill>, 0; mem:LD4[%first1](tbaa=!"any pointer") IntRegs:%vreg7,%vreg1
> STriw_GP <ga:@yy_instr>, 0, %vreg7<kill>; mem:ST4[@yy_instr](tbaa=!"any pointer") IntRegs:%vreg7
> %vreg8<def> = IMPLICIT_DEF; IntRegs:%vreg8
> %R0<def> = COPY %vreg8<kill>; IntRegs:%vreg8
> JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,kill>
>
> Right after the dead vreg is introduced:
>
> # *** IR Dump After Eliminate PHI nodes for reg...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
....end
Predecessors according to CFG: BB#1
%vreg7<def> = LDriw %vreg1<kill>, 0; mem:LD4[%first1](tbaa=!"any
pointer") IntRegs:%vreg7,%vreg1
STriw_GP <ga:@yy_instr>, 0, %vreg7<kill>; mem:ST4[@yy_instr](tbaa=!"any
pointer") IntRegs:%vreg7
%vreg8<def> = IMPLICIT_DEF; IntRegs:%vreg8
%R0<def> = COPY %vreg8<kill>; IntRegs:%vreg8
JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,kill>
Right after the dead vreg is introduced:
# *** IR Dump After Eliminate PHI nodes for register allocation ***:
#...
2011 Mar 26
2
[LLVMdev] Possible missed optimization?
Hello Jakob, thanks for the reply. The three regclasses involved here are
all subsets from each other and aren't disjoint. These are the basic
descriptions of the regclasses involved to show what i mean:
DREGS: R31R30, R29R28 down to R1R0 (16 regs)
DLDREGS: R31R30, R29R28 down to R17R16 (8 regs)
PTRREGS: R31R30, R29R28, R27R26 (3 regs)
All classes intersect each other
2015 Oct 13
2
MachineSink optimization in code containing a setjmp
...It looks like MachineSink will happily move a machine
instruction into a following machine basic block (not necessarily a
successor), even when that later block can be reached through a setjmp.
Here is some example debug output from llc that I'm seeing:
Sinking along critical edge.
Sink instr %vreg8<def,tied1> = ADD64rr %vreg14<tied0>, %vreg31,
%EFLAGS<imp-def,dead>; GR64:%vreg8,%vreg14,%vreg31
into block BB#11:
Predecessors according to CFG: BB#8 BB#10 BB#32
...
EH_SjLj_Setup <BB#36>, <regmask>
Successors according to CFG: BB#34 BB#36
Sin...
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
On Jun 13, 2012, at 10:49 AM, Sergei Larin <slarin at codeaurora.org> wrote:
> So if this early exit is taken:
>
> // SSA defs do not have output/anti dependencies.
> // The current operand is a def, so we have at least one.
> if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
> return;
>
> we do not ever get to this point:
>
>
2013 May 13
1
[LLVMdev] Tracking down a SELECT expansion to predicated moves
...4<def> = MOVIMM21 8; GR:%vreg4
%vreg5<def> = MOV %vreg4<kill>; GR:%vreg5,%vreg4
%vreg6<def> = MOVIMM21 23; GR:%vreg6
%vreg7<def,tied1> = CMOV %vreg5<tied0>, %vreg6<kill>, %vreg3<kill>;
GR:%vreg7,%vreg5,%vreg6 PR:%vreg3
%vreg8<def> = MOVL_GA <ga:@a>; GR:%vreg8
STHri %vreg8<kill>, 0, %vreg7<kill>; mem:ST4[@a] GR:%vreg8,%vreg7
%r8<def> = COPY %vreg2; GR:%vreg2
RET %r31<imp-use>
# End machine code for function main.
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2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
....end
Predecessors according to CFG: BB#1
%vreg7<def> = LDriw %vreg1<kill>, 0; mem:LD4[%first1](tbaa=!"any
pointer") IntRegs:%vreg7,%vreg1
STriw_GP <ga:@yy_instr>, 0, %vreg7<kill>; mem:ST4[@yy_instr](tbaa=!"any
pointer") IntRegs:%vreg7
%vreg8<def> = IMPLICIT_DEF; IntRegs:%vreg8
%R0<def> = COPY %vreg8<kill>; IntRegs:%vreg8
JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,kill>
Right after the dead vreg is introduced:
# *** IR Dump After Eliminate PHI nodes for register allocation ***:
#...
2012 Jun 14
1
[LLVMdev] Assert in live update from MI scheduler.
...edecessors according to CFG: BB#1
> %vreg7<def> = LDriw %vreg1<kill>, 0; mem:LD4[%first1](tbaa=!"any pointer") IntRegs:%vreg7,%vreg1
> STriw_GP <ga:@yy_instr>, 0, %vreg7<kill>; mem:ST4[@yy_instr](tbaa=!"any pointer") IntRegs:%vreg7
> %vreg8<def> = IMPLICIT_DEF; IntRegs:%vreg8
> %R0<def> = COPY %vreg8<kill>; IntRegs:%vreg8
> JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,kill>
>
> Right after the dead vreg is introduced:
>
> # *** IR Dump After Eliminate PHI nodes for reg...
2012 Sep 18
2
[LLVMdev] liveness assertion problem in llc
...ce):
# *** IR Dump Before Calculate spill weights ***:
# Machine code for function CGA_kernel_read: Post SSA
Function Live Ins: %P0 in %vreg5, %P1 in %vreg6
Function Live Outs: %P15
0B BB#0: derived from LLVM BB %entry
Live Ins: %P0 %P1
16B %vreg6<def> = COPY %P1; IntRegs:%vreg6
48B %vreg8<def> = MOV32ri <ga:@fifo>, pred:%noreg; IntRegs:%vreg8 dbg:../src/getbits.c:46:1
64B %vreg9<def> = LDUBri %vreg8, 1, pred:%noreg; mem:LD1[getelementptr inbounds (%struct.FIFO* @fifo, i32 0, i32 1)] IntRegs:%vreg9,%vreg8 dbg:../src/getbits.c:46:1
80B %vreg10<def> = CMPEQI %...
2014 Dec 10
2
[LLVMdev] Virtual register problem in X86 backend
...def>,
%RSP<imp-use>
%vreg6<def> = COPY %EAX; GR32:%vreg6
%vreg4<def> = MOV32ri 0; GR32:%vreg4
MOV64rr %vreg7, %RSP; GR64:%vreg7
Successors according to CFG: BB#1
BB#1: derived from LLVM BB %entry
Predecessors according to CFG: BB#0 BB#2
%vreg8<def> = PHI %vreg7, <BB#0>, %vreg9, <BB#2>;
GR64:%vreg8,%vreg7,%vreg9
CMP64rr %vreg8, %RBP, %EFLAGS<imp-def>; GR64:%vreg8
JE_4 <BB#3>, %EFLAGS<imp-use>
Successors according to CFG: BB#2 BB#3
BB#2: derived from LLVM BB %entry
Predecessors a...
2017 Feb 09
2
Improving the split heuristics for the Greedy Register Allocator
...> 15 Predecessors according to CFG: BB#0
> 16 %vreg6<def> = ADDIStocHA %X2, <ga:@a>; G8RC_and_G8RC_NOX0:%vreg6
> 17 %vreg7<def> = LDtocL <ga:@a>, %vreg6, %X2<imp-use>;
> mem:LD8[GOT] G8RC_and_G8RC_NOX0:%vreg7,%vreg6
> 18 %vreg8<def> = LWA 0, %vreg7;
> mem:LD4[@a](tbaa=!3)(dereferenceable) G8RC:%vreg8 G8RC_and_G8RC_NOX0:%vreg7
> 19 %vreg9<def> = CMPLD %vreg8, %vreg15; CRRC:%vreg9
> G8RC:%vreg8,%vreg15
> 20 BCC 68, %vreg9, <BB#3>; CRRC:%vreg9
> 21 B <BB#2>
&g...
2012 Sep 18
0
[LLVMdev] liveness assertion problem in llc
On Sep 18, 2012, at 1:45 PM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote:
> I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some
2017 Jan 13
2
Improving the split heuristics for the Greedy Register Allocator
...ived from LLVM BB %if.end
15 Predecessors according to CFG: BB#0
16 %vreg6<def> = ADDIStocHA %X2, <ga:@a>; G8RC_and_G8RC_NOX0:%vreg6
17 %vreg7<def> = LDtocL <ga:@a>, %vreg6, %X2<imp-use>;
mem:LD8[GOT] G8RC_and_G8RC_NOX0:%vreg7,%vreg6
18 %vreg8<def> = LWA 0, %vreg7;
mem:LD4[@a](tbaa=!3)(dereferenceable) G8RC:%vreg8 G8RC_and_G8RC_NOX0:%vreg7
19 %vreg9<def> = CMPLD %vreg8, %vreg15; CRRC:%vreg9
G8RC:%vreg8,%vreg15
20 BCC 68, %vreg9, <BB#3>; CRRC:%vreg9
21 B <BB#2>
22 Successors accordin...
2017 Oct 13
2
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...um](tbaa=!4)
G8RC:%vreg2 G8RC_and_G8RC_NOX0:%vreg0
64B %vreg3<def> = LD 0, %vreg1; mem:LD8[%den](tbaa=!4)
G8RC:%vreg3 G8RC_and_G8RC_NOX0:%vreg1
144B %vreg7<def> = LD 8, %vreg0; mem:LD8[%arrayidx.1](tbaa=!4)
G8RC:%vreg7 G8RC_and_G8RC_NOX0:%vreg0
160B %vreg8<def> = LD 8, %vreg1; mem:LD8[%arrayidx2.1](tbaa=!4)
G8RC:%vreg8 G8RC_and_G8RC_NOX0:%vreg1
208B %vreg10<def> = LD 16, %vreg0;
mem:LD8[%arrayidx.2](tbaa=!4) G8RC:%vreg10 G8RC_and_G8RC_NOX0:%vreg0
224B %vreg11<def> = LD 16, %vreg1;
mem:LD8[%arrayidx2.2](tbaa=...
2013 Apr 24
1
[LLVMdev] use of ARM GPRPair register class
...:%vreg5 GPRPair:%vreg9
%vreg6<def> = LDRi12 %vreg3, 120, pred:14, pred:%noreg;
mem:LD4[%arrayidx89](tbaa=!"int") GPR:%vreg6,%vreg3
%vreg7<def> = ADDrr %vreg4<kill>, %vreg5<kill>, pred:14,
pred:%noreg, opt:%noreg; GPR:%vreg7,%vreg4,%vreg5
%vreg8<def> = ADDrr %vreg7<kill>, %vreg6<kill>, pred:14,
pred:%noreg, opt:%noreg; GPR:%vreg8,%vreg7,%vreg6
%R0<def> = COPY %vreg8; GPR:%vreg8
BX_RET pred:14, pred:%noreg, %R0<imp-use>
Thanks,
Ana.
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