Displaying 5 results from an estimated 5 matches for "96d".
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96
2011 Mar 26
2
[LLVMdev] Possible missed optimization?
...so next is what i understood:
********** SIMPLE REGISTER COALESCING **********
********** Function: foo
********** JOINING INTERVALS ***********
entry:
16L %vreg0<def> = COPY %R25R24<kill>; DREGS:%vreg0
Considering merging %vreg0 with physreg %R25R24
RHS = %vreg0 = [16d,96d:0) 0 at 16d
LHS = %R25R24,inf = [0L,16d:0) 0 at 0L-phidef
updated: 96L %vreg8<def> = COPY %R25R24<kill>; PTRREGS:%vreg8
updated: 32L %vreg5<def> = COPY %R25R24; PTRREGS:%vreg5
Joined. Result = %R25R24,inf = [0L,96d:0) 0 at 0L-phidef
32L %vre...
2011 Mar 28
0
[LLVMdev] Possible missed optimization?
...; ********** SIMPLE REGISTER COALESCING **********
> ********** Function: foo
> ********** JOINING INTERVALS ***********
> entry:
> 16L %vreg0<def> = COPY %R25R24<kill>; DREGS:%vreg0
> Considering merging %vreg0 with physreg %R25R24
> RHS = %vreg0 = [16d,96d:0) 0 at 16d
> LHS = %R25R24,inf = [0L,16d:0) 0 at 0L-phidef
> updated: 96L %vreg8<def> = COPY %R25R24<kill>; PTRREGS:%vreg8
> updated: 32L %vreg5<def> = COPY %R25R24; PTRREGS:%vreg5
> Joined. Result = %R25R24,inf = [0L,96d:0) 0 at 0...
2011 Mar 26
0
[LLVMdev] Possible missed optimization?
On Mar 26, 2011, at 1:04 PM, Borja Ferrer wrote:
> Hello Jakob, thanks for the reply. The three regclasses involved here are all subsets from each other and aren't disjoint. These are the basic descriptions of the regclasses involved to show what i mean:
>
> DREGS: R31R30, R29R28 down to R1R0 (16 regs)
> DLDREGS: R31R30, R29R28 down to R17R16 (8 regs)
> PTRREGS:
2011 Mar 26
2
[LLVMdev] Possible missed optimization?
Hello Jakob, thanks for the reply. The three regclasses involved here are
all subsets from each other and aren't disjoint. These are the basic
descriptions of the regclasses involved to show what i mean:
DREGS: R31R30, R29R28 down to R1R0 (16 regs)
DLDREGS: R31R30, R29R28 down to R17R16 (8 regs)
PTRREGS: R31R30, R29R28, R27R26 (3 regs)
All classes intersect each other
2017 Apr 24
3
Debugging UNREACHABLE "Couldn't join subrange" in RegisterCoalescer (out-of-tree backend)
...84B:1)[400B,672r:1) 0 at x 1 at 240r L00000010 [160r,384B:1)[400B,672r:1) 0 at x 1 at 160r L00000002 [480r,480d:1)[496r,672r:0) 0 at 496r 1 at 480r L00000001 [480r,672r:0) 0 at 480r
LHS = %vreg13 [96r,112r:0)[112r,208r:1)[208r,288r:2) 0 at 96r 1 at 112r 2 at 208r L00000002 [96r,96d:1)[112r,288r:0) 0 at 112r 1 at 96r L00000030 [208r,288r:1) 0 at x 1 at 208r L00000001 [96r,288r:0) 0 at 96r
merge %vreg13:2 at 208r into %vreg34:0 at 160r --> @160r
LHST = %vreg13 %vreg13 [96r,112r:0)[112r,208r:1)[208r,288r:2) 0 at 96r 1 at 112r 2 at 208r L000...