llvm dev - May 2017 - Machine instruction verifier pass

Hello Devs,

Machine Instruction verifier pass always validates Live variable info
associated with MachineInstr along with other checks.

Please consider following scenario (w.r.t bugZilla 32583)

1/  MachineCSE pass may prohibit optimising out a common sub-expression for
instruction using physical registers
by looking at the LiveIn info of successor basic blocks.

2/ Which means we need Live Variables analysis to happen prior to executing
MachineCSE.

3/ Live variable analysis associates Kill/def information with
MachineOperands.

4/ In one of the regression Peephole optimizer (which does not uses
liveness information)
performs certain transformations over MachineBasicBlock which potentially
dirties the
liveness information computed early.

5/ Now, when Machine Instruction verifier kicks in after Peephole optimizer
it reports use after kill violation
over a particular instruction.

Can we selectively turn of the live variable checking in Machine
instruction verifier till next Live variable pass is invoked (as per the
need of following pass).

This may sound like defeating the purpose of machine instruction verifier
which checks instruction validity against different parameters after each
transformation pass, but if a pass does not use Live ness information
should not be constrained to do other transformations which may dirty the
live ness information.

Please provide you comments.

Thanks,
Jatin Bhateja
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This kind of sounds like the peephole optimization should really be
resetting the kill flag if it's extending the live range of a [virtual]
register (which is what the description here seems to imply).

On Fri, May 5, 2017 at 9:54 AM, Jatin Bhateja via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Hello Devs,
>
> Machine Instruction verifier pass always validates Live variable info
> associated with MachineInstr along with other checks.
>
> Please consider following scenario (w.r.t bugZilla 32583)
>
> 1/  MachineCSE pass may prohibit optimising out a common sub-expression
> for instruction using physical registers
> by looking at the LiveIn info of successor basic blocks.
>
> 2/ Which means we need Live Variables analysis to happen prior to
> executing MachineCSE.
>
> 3/ Live variable analysis associates Kill/def information with
> MachineOperands.
>
> 4/ In one of the regression Peephole optimizer (which does not uses
> liveness information)
> performs certain transformations over MachineBasicBlock which potentially
> dirties the
> liveness information computed early.
>
> 5/ Now, when Machine Instruction verifier kicks in after Peephole
> optimizer it reports use after kill violation
> over a particular instruction.
>
> Can we selectively turn of the live variable checking in Machine
> instruction verifier till next Live variable pass is invoked (as per the
> need of following pass).
>
> This may sound like defeating the purpose of machine instruction verifier
> which checks instruction validity against different parameters after each
> transformation pass, but if a pass does not use Live ness information
> should not be constrained to do other transformations which may dirty the
> live ness information.
>
> Please provide you comments.
>
> Thanks,
> Jatin Bhateja
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
>
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- Please do not add any more uses of the LiveVariables pass! It is deprecated
and only kept around for one last pass that isn't converted. All new code
should use LiveIntervalAnalysis!
- Kill flags are optional: If they are present they must be correct, but it is
legal to have a value die without having a kill flag on the operand. So often a
simple fix is to clear out the kill flags from instructions you touch instead of
recomputing them. The only downside is that some later passes will only perform
the maximum amount of optimization will kill flags present [1]

- Matthias

[1] Long term we want to get rid of kill flags completely which should clean up
a lot of code. But that is unfortunately a very tedious process, last time I
tried to switch the biggest user of killflags (RegisterScavenger) to a new
algorithm a powerpc stage2 buildbot broke and I never figured out why...
> On May 17, 2017, at 11:29 AM, Nemanja Ivanovic via llvm-dev <llvm-dev at
lists.llvm.org> wrote:
> 
> This kind of sounds like the peephole optimization should really be
resetting the kill flag if it's extending the live range of a [virtual]
register (which is what the description here seems to imply).
> 
> On Fri, May 5, 2017 at 9:54 AM, Jatin Bhateja via llvm-dev <llvm-dev at
lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
> Hello Devs,
> 
> Machine Instruction verifier pass always validates Live variable info
associated with MachineInstr along with other checks.
> 
> Please consider following scenario (w.r.t bugZilla 32583)
> 
> 1/  MachineCSE pass may prohibit optimising out a common sub-expression for
instruction using physical registers
> by looking at the LiveIn info of successor basic blocks. 
> 
> 2/ Which means we need Live Variables analysis to happen prior to executing
MachineCSE.
> 
> 3/ Live variable analysis associates Kill/def information with
MachineOperands.
> 
> 4/ In one of the regression Peephole optimizer (which does not uses
liveness information)
> performs certain transformations over MachineBasicBlock which potentially
dirties the
> liveness information computed early. 
> 
> 5/ Now, when Machine Instruction verifier kicks in after Peephole optimizer
it reports use after kill violation
> over a particular instruction.  
> 
> Can we selectively turn of the live variable checking in Machine
instruction verifier till next Live variable pass is invoked (as per the need of
following pass).
> 
> This may sound like defeating the purpose of machine instruction verifier
which checks instruction validity against different parameters after each
transformation pass, but if a pass does not use Live ness information should not
be constrained to do other transformations which may dirty the live ness
information.
> 
> Please provide you comments.
> 
> Thanks,
> Jatin Bhateja
> 
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
<http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev>
> 
> 
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
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