similar to: Machine instruction verifier pass

- Please do not add any more uses of the LiveVariables pass! It is deprecated and only kept around for one last pass that isn't converted. All new code should use LiveIntervalAnalysis! - Kill flags are optional: If they are present they must be correct, but it is legal to have a value die without having a kill flag on the operand. So often a simple fix is to clear out the kill flags from

Other suggestions 1/ Write a separate MI pass to split the macro MI which was generated earlier as a result of ISel to multiple MIs. 2/ Take the decision of splitting later in the pipeling during MC lowering. Decision about when you need to split should be driven by your intent to do any further processing over constituent instruction. ~ Jatin On Fri, Mar 2, 2018 at 8:19 PM, Jatin Bhateja

Guys, Do we have any LLVM social for India/Asia. Wonderful concept to meet fellow community members and have technical discussion. Cheers, Jatin -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180503/ce896912/attachment.html>

Seems llvm cannot pass metadata to MachineInstr, or setting operand description in class Instruction and pass to class MachineInstr. Is it a good idea to extend llvm kernel structure to having this feature? Jonathan > On Nov 27, 2017, at 9:01 PM, Jatin Bhateja <jatin.bhateja at gmail.com> wrote: > > SelectionDAGBuilder contained within SelectionDAGISel has a map (NodeMap) b/w

No but we should think of arranging one. On Thu, May 3, 2018, 8:27 PM Jatin Bhateja via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Guys, > > Do we have any LLVM social for India/Asia. > > Wonderful concept to meet fellow community members and have technical > discussion. > > Cheers, > Jatin > _______________________________________________ > LLVM

Hello Devs, I am getting following error while connecting to review server. " A Troublesome Encounter! Woe! This request had its journey cut short by unexpected circumstances (Can Not Connect to MySQL)" Is anyone else facing this? Thanks [image: Inline image 1] -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi Nagaraju, Few suggestions split this into following steps. 1/ DAG Legalization : Custom lower the instruction (branch in your case) appropriately in legalization to target specific DAG nodes and glue the nodes together which you want scheduler should schedule together. 2/ Instruction Selection : Define patterns to match the custom DAG nodes. Thus actual decision of creating multiple

Hi All, I am working on a target which requires to generated two instructions for a single branch instruction. ex: imm 1 br r4,0xabcd branch address is 0x1abcd, imm has the upper 16 bits and br has lower 16 bits. Can anyone let me know how to write these kind of patterns in the InstrInfo.td file. Thanks in Advance, Nagaraju

Am 07.10.2010 um 19:50 schrieb Chris Lattner: > > On Oct 6, 2010, at 6:16 PM, Gabor Greif wrote: > >> Hi all, >> >> I am slowly working on a SwitchInst optimizer (http://llvm.org/ >> PR8125) >> and now I am running into a deficiency of the x86 >> peephole optimizer (or jump-threader?). Here is what I get: >> >> >> andl $3,

I am working on llvm gpu backend. The instruction metadata can only get in IR (class instruction). In DAG stage, the instructions are reordered, so I cannot map the metadata to correct instruction if I cannot access instruction from DAG or MachineInstr structure. > On Nov 26, 2017, at 11:02 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > It might be a more useful to know what

Hi all, I am slowly working on a SwitchInst optimizer (http://llvm.org/PR8125) and now I am running into a deficiency of the x86 peephole optimizer (or jump-threader?). Here is what I get: andl $3, %edi je .LBB0_4 # BB#2: # %nz # in Loop: Header=BB0_1 Depth=1 cmpl $2, %edi

Hi Hashim, Scalar evolution determines evolution of scalar in terms of expression chain driving it. Try dumping the detailed log using opt -analyze -scalar-evolution <.ll> -S , and look for LoopDispositions corresponding to different expression which shows variance characteristics of a particular expression w.r.t loop i.e. [computable/variant/invariant]. Thanks On Fri, Dec 1, 2017 at

Hi, I am using Scalar Evolution to extract access expressions (for load and store instructions) in terms of the loop induction variables. I observe that the Scalar Evolution analysis is returning more expressions than I expect - including ones that are not defined in terms of the loop induction variable. For instance in the following code: for(unsigned long int bid = 0; bid < no_of_queries;

On Oct 6, 2010, at 6:16 PM, Gabor Greif wrote: > Hi all, > > I am slowly working on a SwitchInst optimizer (http://llvm.org/PR8125) > and now I am running into a deficiency of the x86 > peephole optimizer (or jump-threader?). Here is what I get: > > > andl $3, %edi > je .LBB0_4 > # BB#2: # %nz >

On Oct 13, 2010, at 11:22 AM, Gabor Greif wrote: > Hi Chris, > > I had a look into MachineCSE, but it looks like MBB-oriented. > The above problem is an inter-block one. Also MCSE seems > to perform value numbering on virtual/physical registers, which > does not map very well to status register bits that are implicitly > defined. > Any chance to recast this issue as a

Hi Medhi, > On Dec 11, 2015, at 6:18 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: > > Hi, > > Side note: shouldn’t RFCs rather go to llvm-dev? You’re right! I could have sworn I have sent it to llvm-dev! Moving it now. > >> On Dec 11, 2015, at 5:44 PM, Quentin Colombet via llvm-commits <llvm-commits at lists.llvm.org> wrote: >> >> Hi,

Hi, I've been looking at improving atomicrmw & cmpxchg code more, particularly on architectures using the load-linked/store-conditional model. The summary is that current expansion for cmpxchg seems to happen too late for LLVM to make meaningful use of the opportunities it provides. I'd like to move it earlier and express it in terms of a first-class pair of "load linked"

Hi, My target has a special configuration register that many instructions read implicitly, configuring for example if an add instruction should saturate at over/underflow or not. Now, I have a problem where the MachineCSE removes a setting of this configuration register in a basic block, because MachineCSE::isPhysDefTriviallyDead can't find any uses of it in the basic block where

On 7/4/2015 1:07 PM, John R Pierce wrote: > On 7/4/2015 12:28 AM, Jatin Davey wrote: >>> >> My server supports ACPI 4.0 standard , Will that be helpful ? > > does `init 0` as a root command cause it to gracefully shut down and > power off ? thats all the ACPI support you need. [Jatin] Yes, init 0 does gracefully shutdown the server and power off. > > >

Hi I have a linux box which has CentOS running in it. I logged into the box using root and wrote a script in the /home/proc_threads directory. saved the file and quit. I changed the file permissions such that any user could execute it using the "chmod 777 filename" command. When i log out and log in as a non-root user i was not able to execute the script though. Could some one