search for: bhateja

...arlier as a result of ISel to multiple MIs. 2/ Take the decision of splitting later in the pipeling during MC lowering. Decision about when you need to split should be driven by your intent to do any further processing over constituent instruction. ~ Jatin On Fri, Mar 2, 2018 at 8:19 PM, Jatin Bhateja <jatin.bhateja at gmail.com> wrote: > Hi Nagaraju, > > Few suggestions split this into following steps. > > 1/ DAG Legalization : Custom lower the instruction (branch in your case) > appropriately in legalization to target specific DAG nodes and glue the > nodes together...

Seems llvm cannot pass metadata to MachineInstr, or setting operand description in class Instruction and pass to class MachineInstr. Is it a good idea to extend llvm kernel structure to having this feature? Jonathan > On Nov 27, 2017, at 9:01 PM, Jatin Bhateja <jatin.bhateja at gmail.com> wrote: > > SelectionDAGBuilder contained within SelectionDAGISel has a map (NodeMap) b/w Value (Instruction) and corrosponding dag value (SDValue). > > Isn't that usable for your purpose. > > Thanks, > Jatin > > On 27 Nov 2017 18...

Guys, Do we have any LLVM social for India/Asia. Wonderful concept to meet fellow community members and have technical discussion. Cheers, Jatin -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180503/ce896912/attachment.html>

No but we should think of arranging one. On Thu, May 3, 2018, 8:27 PM Jatin Bhateja via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Guys, > > Do we have any LLVM social for India/Asia. > > Wonderful concept to meet fellow community members and have technical > discussion. > > Cheers, > Jatin > _______________________________________________...

Hello Devs, I am getting following error while connecting to review server. " A Troublesome Encounter! Woe! This request had its journey cut short by unexpected circumstances (Can Not Connect to MySQL)" Is anyone else facing this? Thanks [image: Inline image 1] -------------- next part -------------- An HTML attachment was scrubbed... URL:

...tion verifier which checks instruction validity against different parameters after each transformation pass, but if a pass does not use Live ness information should not be constrained to do other transformations which may dirty the live ness information. Please provide you comments. Thanks, Jatin Bhateja -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170505/456555a2/attachment.html>

...-dev at lists.llvm.org> wrote: > > This kind of sounds like the peephole optimization should really be resetting the kill flag if it's extending the live range of a [virtual] register (which is what the description here seems to imply). > > On Fri, May 5, 2017 at 9:54 AM, Jatin Bhateja via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > Hello Devs, > > Machine Instruction verifier pass always validates Live variable info associated with MachineInstr along with other checks. > > Please consider following scenario (w.r...

Hi Nagaraju, Few suggestions split this into following steps. 1/ DAG Legalization : Custom lower the instruction (branch in your case) appropriately in legalization to target specific DAG nodes and glue the nodes together which you want scheduler should schedule together. 2/ Instruction Selection : Define patterns to match the custom DAG nodes. Thus actual decision of creating multiple

Hi Hashim, Scalar evolution determines evolution of scalar in terms of expression chain driving it. Try dumping the detailed log using opt -analyze -scalar-evolution <.ll> -S , and look for LoopDispositions corresponding to different expression which shows variance characteristics of a particular expression w.r.t loop i.e. [computable/variant/invariant]. Thanks On Fri, Dec 1, 2017 at

I am working on llvm gpu backend. The instruction metadata can only get in IR (class instruction). In DAG stage, the instructions are reordered, so I cannot map the metadata to correct instruction if I cannot access instruction from DAG or MachineInstr structure. > On Nov 26, 2017, at 11:02 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > It might be a more useful to know what

Hi All, I am working on a target which requires to generated two instructions for a single branch instruction. ex: imm 1 br r4,0xabcd branch address is 0x1abcd, imm has the upper 16 bits and br has lower 16 bits. Can anyone let me know how to write these kind of patterns in the InstrInfo.td file. Thanks in Advance, Nagaraju

Hi, I am using Scalar Evolution to extract access expressions (for load and store instructions) in terms of the loop induction variables. I observe that the Scalar Evolution analysis is returning more expressions than I expect - including ones that are not defined in terms of the loop induction variable. For instance in the following code: for(unsigned long int bid = 0; bid < no_of_queries;

...h by Daniel Marjamäki. * "This is regarding addition of a new priority selector/heuristic for Scheduler DAG based scheduling. It adds a heuristic to pickup next instruction to schedule if its operands have already been scheduled." [D34596](https://reviews.llvm.org/D34596), patch by Jatin Bhateja. ## LLVM commits * An initial version of a new llvm-cfi-verify tool has landed. It intends to help verify protections inserted by LLVM's control-flow integrity schemes. [r313809](http://reviews.llvm.org/rL313809). * The BPF backend gained inline asm support [rL313593](http://reviews.llvm.or...

Hello Devs, I'm experiencing a delay in mails being received from llvm-commits and llvm-devl list. Is there some issue with the servers. Thanks, Jatin -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170926/7c75bdfc/attachment.html>

Hi Ivan, Matcher table generation which is implemented in utils/DAGISelEmitter.cpp does use heusiristics like number of instructions which a pattern will cover, latency (not the one which Targets scheduling defines) while emitting the candidate patterns for a give dag node. Current implications may not be implication of algorithm in toto though. Thanks, Jatin On Wednesday, March 28, 2018, Ivan