llvm dev - Aug 2017 - callee saved regs list

Hi,

It has been discovered recently that it is needed for the SystemZ 
backend to add super-regs to the callee saved regs list like:

  def CSR_SystemZ : CalleeSavedRegs<(add (sequence "R%dD", 6, 15),
-                                       (sequence "F%dD", 8, 15))>;
+                                       [R6Q, R8Q, R10Q, R12Q, R14Q],
+                                       (sequence "F%dD", 8, 15),
+                                       [F8Q, F9Q, F12Q, F13Q])>;

(Q => 128 bits)

It seems strange that the common code cannot deduce for itself that the 
super regs are also callee saved given that all sub-regs of a register are.

Are other targets adding super-regs as well like this? Could / should 
this be fixed?

Thanks to Wei Mi for helping to point this out.

/Jonas

In our SHAVE target we use 2 x 32-bit scalar consecutive physical register pairs
as super-registers to allow us to efficiently load and store 'i64' and
'f64' values.  This has been troublesome though, and we have had to make
several patches to our code as we discovered that both register-liveness and
callee-saved registers could be broken by other assumptions in LLVM.  Having
this handled by the general code would reduce the number of special-cases that
we have to add, and presumably other targets that use super-registers such as
SystemZ.

    MartinO

-----Original Message-----
From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Jonas
Paulsson via llvm-dev
Sent: Thursday, August 17, 2017 11:07 AM
To: llvm-dev <llvm-dev at lists.llvm.org>
Cc: Ulrich Weigand <ulrich.weigand at de.ibm.com>; Wei Mi <wmi at
google.com>
Subject: [llvm-dev] callee saved regs list

Hi,

It has been discovered recently that it is needed for the SystemZ backend to add
super-regs to the callee saved regs list like:

  def CSR_SystemZ : CalleeSavedRegs<(add (sequence "R%dD", 6, 15),
-                                       (sequence "F%dD", 8, 15))>;
+                                       [R6Q, R8Q, R10Q, R12Q, R14Q],
+                                       (sequence "F%dD", 8, 15),
+                                       [F8Q, F9Q, F12Q, F13Q])>;

(Q => 128 bits)

It seems strange that the common code cannot deduce for itself that the super
regs are also callee saved given that all sub-regs of a register are.

Are other targets adding super-regs as well like this? Could / should this be
fixed?

Thanks to Wei Mi for helping to point this out.

/Jonas

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On 8/17/2017 5:07 AM, Jonas Paulsson via llvm-dev wrote:
> It seems strange that the common code cannot deduce for itself that the 
> super regs are also callee saved given that all sub-regs of a register are.
For this to be true, the super-register needs to be covered by its 
sub-registers.  This is not the case in general (e.g. X86).  Also, if 
you have a multi-level sub-register hierarchy then you may not need all 
sub-registers to cover a given register.

Out of the users of the callee-saved information, LivePhysRegs should 
handle the liveness properly.

-Krzysztof

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
hosted by The Linux Foundation

On 2017-08-17 15:48, Krzysztof Parzyszek via llvm-dev
wrote:
> On 8/17/2017 5:07 AM, Jonas Paulsson via llvm-dev wrote:
>> It seems strange that the common code cannot deduce for itself that 
>> the super regs are also callee saved given that all sub-regs of a 
>> register are.
>
> For this to be true, the super-register needs to be covered by its 
> sub-registers.  This is not the case in general (e.g. X86).  Also, if 
> you have a multi-level sub-register hierarchy then you may not need 
> all sub-registers to cover a given register.
>
On SystemZ, the super-registers in question are indeed completely 
covered by its sub-registers in the callee-saved list: R6Q = R6 + R7, etc.

/Jonas