Displaying 9 results from an estimated 9 matches for "calleesavedregs".
2012 Jun 24
4
[LLVMdev] Request for merge: GHC/ARM calling convention.
...ersion. (For those interested,
the error with empty list was "expected identifier in dag init")
+// GHC set of callee saved regs is empty as all those regs are
+// used for passing STG regs around
+// sub/add LR is a workaround for not being able to compile empty list:
+// def CSR_GHC : CalleeSavedRegs<()>;
+def CSR_GHC : CalleeSavedRegs<(sub (add LR), LR)>;
otherwise, the patch is the same like it was merged into 3.0 release as
submitted here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-October/044173.html
Please see attached patch and tell me if it's all right for inclus...
2012 Dec 07
0
[LLVMdev] Increase the number of registers in ARM
...work. I am going
> to compile and run it now.
We have done the similar work[1] on this topic by gcc and we have
start migrate our platform to LLVM.
In my experience, you need to take care the follow part:
* ARMBaseRegisterInfo::getRegPressureLimit
* ARMBaseRegisterInfo::getRawAllocationOrder
* CalleeSavedRegs
* ARMFrameLowering::emitPrologue
[1] Doubling the Number of Registers on ARM Processors
http://aces.snu.ac.kr/interact-16/papers/interact-16-paper-1.pdf
2012 Aug 01
0
[LLVMdev] Request for merge: GHC/ARM calling convention.
...ested, the error with empty list was "expected identifier in dag init")
>
> +// GHC set of callee saved regs is empty as all those regs are
> +// used for passing STG regs around
> +// sub/add LR is a workaround for not being able to compile empty list:
> +// def CSR_GHC : CalleeSavedRegs<()>;
> +def CSR_GHC : CalleeSavedRegs<(sub (add LR), LR)>;
>
> otherwise, the patch is the same like it was merged into 3.0 release as submitted here: http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-October/044173.html
>
> Please see attached patch and tell me if it'...
2012 Dec 07
2
[LLVMdev] Increase the number of registers in ARM
I almost change all the instruction formats. It was a huge work. I am going
to compile and run it now.
Best Regards,
A. Yazdanbakhsh
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
PhD. Student
School of Electrical and Computer Engineering
University of Wisconsin-Madison
E-mail: yazdanbakhsh
2017 Aug 17
3
callee saved regs list
Hi,
It has been discovered recently that it is needed for the SystemZ
backend to add super-regs to the callee saved regs list like:
def CSR_SystemZ : CalleeSavedRegs<(add (sequence "R%dD", 6, 15),
- (sequence "F%dD", 8, 15))>;
+ [R6Q, R8Q, R10Q, R12Q, R14Q],
+ (sequence "F%dD", 8, 15),
+...
2019 Jan 15
4
[RFC] Introducing an explicit calling convention
David Chisnall via llvm-dev <llvm-dev at lists.llvm.org> writes:
> I'm not opposed to this in principle, and actually I'd quite like to
> move in this direction and remove our reliance on undocumented and
> inconsistent conventions between the back end and the front end for
> conveying information about ABIs. For example, returning two 32-bit
> integers or a pair of
2012 Feb 28
0
[LLVMdev] Register mask operands
...sters.
Currently, only the ARM and X86 targets have been converted to use register masks. Owners of the other targets in the tree should consider converting as well.
The conversion is quite simple, copy from ARM and X86 as needed:
- Move callee saved register lists to *CallingConv.td by defining CalleeSavedRegs instances. TableGen will produce *_SaveList and *_RegMask arrays. Use them to implement the TRI::getCalleeSavedRegs() and TRI::getCallPreservedRegMask() hooks.
- Fix target-dependent code to understand regmask operands. The target-independent passes have already been fixed.
- Update *TargetLoweri...
2019 Apr 26
10
Automatically backing up and restoring x18 around function calls on AArch64?
Hi,
When using Wine to run Windows ARM64 executables on Linux, there's one
major ABI incompatibility between the two; Windows treats the x18
register as the reserved platform register, while it is free to be
clobbered anywhere in code on Linux.
The Wine code sets up this register before passing control over to the
Windows executable code, but whenever the Windows code calls a function
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...e Hexagon::POST_STdri_cNotPt:
>> + case Hexagon::POST_STdri_cdnPt_V4:
>> + case Hexagon::POST_STdri_cdnNotPt_V4:
>> + return true;
>> +
>> + default:
>> + return false;
>> + }
>> +}
>> +
>> +bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
>> + return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
>> +}
>>
>> bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
>> bool isPred = MI->getDesc().isPredicable();
>> @@ -559,6 +1414,7 @@ bool...