Intel recently release a new tsc adjust feature at latest SDM 17.13.3.
CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is supported.
Basically it is used to simplify TSC synchronization, operation of
IA32_TSC_ADJUST MSR is as follows:
1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0;
2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or
subtracts)
value X from the TSC, the logical processor also adds (or subtracts) value X
from the IA32_TSC_ADJUST MSR;
3). If an execution of WRMSR to the IA32_TSC_ADJUST MSR adds (or subtracts)
value X from that MSR, the logical processor also adds (or subtracts) value
X
from the TSC;
With it, OS would be easier when sync tsc.
Thanks,
Jinsong
On 20/09/2012 09:06, "Liu, Jinsong" <jinsong.liu@intel.com> wrote:> Intel recently release a new tsc adjust feature at latest SDM 17.13.3. > CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is supported. > > Basically it is used to simplify TSC synchronization, operation of > IA32_TSC_ADJUST MSR is as follows: > 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0; > 2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or > subtracts) > value X from the TSC, the logical processor also adds (or subtracts) value > X > from the IA32_TSC_ADJUST MSR; > 3). If an execution of WRMSR to the IA32_TSC_ADJUST MSR adds (or subtracts) > value X from that MSR, the logical processor also adds (or subtracts) > value X > from the TSC; > > With it, OS would be easier when sync tsc.Actually it appears to strictly add code to, and hence complicate, the hypervisor. So how exactly is it beneficial? -- Keir> Thanks, > Jinsong
>>> On 20.09.12 at 10:16, Keir Fraser <keir@xen.org> wrote: > On 20/09/2012 09:06, "Liu, Jinsong" <jinsong.liu@intel.com> wrote: > >> Intel recently release a new tsc adjust feature at latest SDM 17.13.3. >> CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is supported. >> >> Basically it is used to simplify TSC synchronization, operation of >> IA32_TSC_ADJUST MSR is as follows: >> 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0; >> 2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or >> subtracts) >> value X from the TSC, the logical processor also adds (or subtracts) > value >> X >> from the IA32_TSC_ADJUST MSR; >> 3). If an execution of WRMSR to the IA32_TSC_ADJUST MSR adds (or subtracts) >> value X from that MSR, the logical processor also adds (or subtracts) >> value X >> from the TSC; >> >> With it, OS would be easier when sync tsc. > > Actually it appears to strictly add code to, and hence complicate, the > hypervisor. So how exactly is it beneficial?It''s beneficial to the guest if I''m not mistaken, for precisely the purpose that patch 2 doesn''t address for the hypervisor in spite of its title (see my response there). Jan
Jan Beulich wrote:>>>> On 20.09.12 at 10:16, Keir Fraser <keir@xen.org> wrote: >> On 20/09/2012 09:06, "Liu, Jinsong" <jinsong.liu@intel.com> wrote: >> >>> Intel recently release a new tsc adjust feature at latest SDM >>> 17.13.3. CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is >>> supported. >>> >>> Basically it is used to simplify TSC synchronization, operation of >>> IA32_TSC_ADJUST MSR is as follows: >>> 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0; >>> 2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR >>> adds (or subtracts) value X from the TSC, the logical processor >>> also adds (or subtracts) value X from the IA32_TSC_ADJUST MSR; >>> 3). If an execution of WRMSR to the IA32_TSC_ADJUST MSR adds (or >>> subtracts) value X from that MSR, the logical processor also >>> adds (or subtracts) value X from the TSC; >>> >>> With it, OS would be easier when sync tsc. >> >> Actually it appears to strictly add code to, and hence complicate, >> the hypervisor. So how exactly is it beneficial? > > It''s beneficial to the guest if I''m not mistaken, for precisely the > purpose that patch 2 doesn''t address for the hypervisor in spite > of its title (see my response there). > > JanYes, updated accordingly w/ more clear comments and would send later. Thanks, Jinsong
Keir Fraser wrote:> On 20/09/2012 09:06, "Liu, Jinsong" <jinsong.liu@intel.com> wrote: > >> Intel recently release a new tsc adjust feature at latest SDM >> 17.13.3. CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is >> supported. >> >> Basically it is used to simplify TSC synchronization, operation of >> IA32_TSC_ADJUST MSR is as follows: >> 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0; >> 2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds >> (or subtracts) value X from the TSC, the logical processor also >> adds (or subtracts) value X from the IA32_TSC_ADJUST MSR; >> 3). If an execution of WRMSR to the IA32_TSC_ADJUST MSR adds (or >> subtracts) value X from that MSR, the logical processor also >> adds (or subtracts) value X from the TSC; >> >> With it, OS would be easier when sync tsc. > > Actually it appears to strictly add code to, and hence complicate, the > hypervisor. So how exactly is it beneficial? > > -- Keir >The benefit of these patches are for hvm guest. The comments in SDM may best explain why guest like the feature: ==================Software can modify the value of the time-stamp counter (TSC) of a logical processor by using the WRMSR instruction to write to the IA32_TIME_STAMP_COUNTER MSR (address 10H). Because such a write applies only to that logical processor, software seeking to synchronize the TSC values of multiple logical processors must perform these writes on each logical processor. It may be difficult for software to do this in a way than ensures that all logical processors will have the same value for the TSC at a given point in time. ================== IMO tsc adjust provide another way to update tsc, but better than directly update IA32_TIME_STAMP_COUNTER MSR, since with tsc adjust logical processor can individually adjust tsc on its convenient time. Thanks, Jinsong