search for: msr

The "APIC-register virtualization" and "virtual-interrupt deliver" VM-execution control has no effect on the behavior of RDMSR/WRMSR if the "virtualize x2APIC mode" VM-execution control is 0. When guest uses x2APIC mode, we should enable "virtualize x2APIC mode" for APICV first. Signed-off-by: Jiongxi Li <jiongxi.li@intel.com> diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs....

From: Mihai Don?u <mdontu at bitdefender.com> This command is used to enable/disable introspection for a specific MSR. The KVMI_EVENT_MSR event is sent when the tracked MSR is going to be changed. The introspection tool can respond by allowing the guest to continue with normal execution or by discarding the change. This is meant to prevent malicious changes to MSRs such as MSR_IA32_SYSENTER_EIP. Signed-off-by: M...

From: Mihai Don?u <mdontu at bitdefender.com> This command is used to enable/disable introspection for a specific MSR. The KVMI_EVENT_MSR event is send when the tracked MSR is going to be changed. The introspection tool can respond by allowing the guest to continue with normal execution or by discarding the change. This is meant to prevent malicious changes to MSRs such as MSR_IA32_SYSENTER_EIP. Signed-off-by: M...

From: Nicu?or C??u <ncitu at bitdefender.com> This commit also ensures that the introspection tool and the userspace do not disable each other the MSR access VM-exit. Signed-off-by: Nicu?or C??u <ncitu at bitdefender.com> Signed-off-by: Adalbert Laz?r <alazar at bitdefender.com> --- arch/x86/include/asm/kvmi_host.h | 12 ++++ arch/x86/kvm/kvmi.c | 119 +++++++++++++++++++++++++++---- arch/x86/kvm/svm.c |...

Hello, This series of patches integrates msr.h header. What it really does, is a series of steps to allow us to get rid of duplicate code between i386 and x86_64 versions With this done, achieving paravirt for x86_64 gets really easy, just a couple of extra code. The first patch was already sent a while ago, but was not yet pushed to any tr...

Hello, This series of patches integrates msr.h header. What it really does, is a series of steps to allow us to get rid of duplicate code between i386 and x86_64 versions With this done, achieving paravirt for x86_64 gets really easy, just a couple of extra code. The first patch was already sent a while ago, but was not yet pushed to any tr...

Add the new MEM_EVENT_REASON_MSR event type. Works similarly to the other register events, except event.gla always contains the MSR type (in addition to event.gfn, which holds the value). Signed-off-by: Razvan Cojocaru <rzvncj@gmail.com> Acked-by: Tim Deegan <tim@xen.org> diff -r b04de677de31 -r e33d3d37dfbf xen/arch...

Intel recently release a new tsc adjust feature at latest SDM 17.13.3. CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is supported. Basically it is used to simplify TSC synchronization, operation of IA32_TSC_ADJUST MSR is as follows: 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0; 2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or subtracts) value X from the TSC, the logica...

From: Mihai Don?u <mdontu at bitdefender.com> The KVMI_CONTROL_MSR is used to enable/disable introspection for a specific MSR. The KVMI_EVENT_MSR is send when the tracked MSR is going to be changed. The introspection tool can respond by allowing the guest to continue with normal execution or by discarding the change. This is meant to prevent malicious changes to...

...gt; >> So, as a concrete straw-man: >> >> CPUID leaf 0x48000000 would return a maximum leaf number in EAX (e.g. >> 0x48000001) along with a signature value (e.g. "CrossHVPara\0") in >> EBX, ECX, and EDX. >> >> CPUID 0x48000001.EAX would contain an MSR number to read to get a >> random number if supported and zero if not supported. >> >> Questions: >> >> 1. Can we use a fixed MSR number? This would be a little bit simpler, >> but it would depend on getting a wider MSR range from Intel. >> > > Why d...

...gt; >> So, as a concrete straw-man: >> >> CPUID leaf 0x48000000 would return a maximum leaf number in EAX (e.g. >> 0x48000001) along with a signature value (e.g. "CrossHVPara\0") in >> EBX, ECX, and EDX. >> >> CPUID 0x48000001.EAX would contain an MSR number to read to get a >> random number if supported and zero if not supported. >> >> Questions: >> >> 1. Can we use a fixed MSR number? This would be a little bit simpler, >> but it would depend on getting a wider MSR range from Intel. >> > > Why d...

Fairly straightforward code motion of MSR / TSC / PMC accessors to the sub-arch level. Note that rdmsr/wrmsr_safe functions are not moved; Linux relies on the fault behavior here in the event that certain MSRs are not supported on hardware, and combining this with a VMI wrapper is overly complicated. The instructions are virtualizable wi...

Fairly straightforward code motion of MSR / TSC / PMC accessors to the sub-arch level. Note that rdmsr/wrmsr_safe functions are not moved; Linux relies on the fault behavior here in the event that certain MSRs are not supported on hardware, and combining this with a VMI wrapper is overly complicated. The instructions are virtualizable wi...

...I'm still keeping a samba servers to make my cups-managed printers available to windows users, rather than duplicating configuration with a Windows print service. But I'm facing two problems, probably due to the way we manage AD. First, all my host belong to a Unix-managed DNS domain (msr-inria.inria.fr), not to the windows-managed one corresponding to the AD realm (msr-inria.idf). It means resolving their IP address result in foo.msr-inria.inria.fr, not in foo.msr-inria.idf. The Unix DNS is a secondary server for the foo.msr-inria.idf, meaning SRV record lookup still works. But...

When CONFIG_PARAVIRT is enabled, the kernel is ignoring exceptions on the {rd,wr}msr instructions. This makes serious issues (either on the guest kernel, or on the host) be silently ignored, and is different from the native MSR code (which does not ignore the exceptions). As paravirt.h already includes linux/bug.h, I don't see what was the original issue preventing BUG_ON from...

When CONFIG_PARAVIRT is enabled, the kernel is ignoring exceptions on the {rd,wr}msr instructions. This makes serious issues (either on the guest kernel, or on the host) be silently ignored, and is different from the native MSR code (which does not ignore the exceptions). As paravirt.h already includes linux/bug.h, I don't see what was the original issue preventing BUG_ON from...

hpa pointed out that the ABI that I chose (an MSR from the KVM range and a KVM cpuid bit) is unnecessarily KVM-specific. It would be nice to allocate an MSR that everyone involved can agree on and, rather than relying on a cpuid bit, just have the guest probe for the MSR. This leads to a few questions: 1. How do we allocate an MSR? (For backgr...

hpa pointed out that the ABI that I chose (an MSR from the KVM range and a KVM cpuid bit) is unnecessarily KVM-specific. It would be nice to allocate an MSR that everyone involved can agree on and, rather than relying on a cpuid bit, just have the guest probe for the MSR. This leads to a few questions: 1. How do we allocate an MSR? (For backgr...

plain text document attachment (xx-paravirt-msr-header.patch) Code consolidations of msr routines for paravirt ops. Signed-off-by: Steven Rostedt srostedt@redhat.com Signed-off-by: Glauber de Oliveira Costa <gcosta@redhat.com> Index: clean-start/include/asm-x86_64/msr.h ==================================================================...

plain text document attachment (xx-paravirt-msr-header.patch) Code consolidations of msr routines for paravirt ops. Signed-off-by: Steven Rostedt srostedt@redhat.com Signed-off-by: Glauber de Oliveira Costa <gcosta@redhat.com> Index: clean-start/include/asm-x86_64/msr.h ==================================================================...