Xen devel - Apr 2007 - Question regarding the number of P2M l3e entries

In p2m.c (line 197 and line 550), the code assumes the number of L3 P2M
table entries is 8 (under PAE mode). According to Intel and AMD specs,
it is 4. Could someone explain this discrepancy? Is it a bug?
 
-Wei


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See the comment just above line 197. The P2M is a special Œextended¹ PAE
pagetable with double the number of top-level slots. This gives PAE guests
an 8GB pseudophysical address space. OF course if the P2M is actually used
as a shadow pagetable (i.e., because an HVM guest has paging disabled) then
only the first four slots will be used for the shadow pagetable, and only
the first 4GB of the pseuodphysical address space will be accessible from
guest context.

 -- Keir

On 3/4/07 07:25, "Huang2, Wei" <Wei.Huang2@amd.com> wrote:
> In p2m.c (line 197 and line 550), the code assumes the number of L3 P2M
table
> entries is 8 (under PAE mode). According to Intel and AMD specs, it is 4.
> Could someone explain this discrepancy? Is it a bug?
>  
> -Wei
> 
> 
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xensource.com
> http://lists.xensource.com/xen-devel



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> In p2m.c (line 197 and line 550), the code assumes the number 
> of L3 P2M table entries is 8 (under PAE mode). According to 
> Intel and AMD specs, it is 4. Could someone explain this 
> discrepancy? Is it a bug?
The P2M table maps guest physical addresses to machine addresses. 32b
PAE guests may have up to 8GB of RAM on current 32b Xen, hence 8 slots.
On 64b Xen you can give them the PAE max of 64GB RAM (in fact, you could
actually give them more than 64GB as the physical address width limit no
longer applies -- you might have to hack the guest to accept the RAM,
though).

Ian

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