similar to: [LLVMdev] Need Help Understanding Operands in X86 MachineFunctionPass

On Sep 11, 2012, at 10:57 AM, John Criswell wrote: > I'm working on an X86 MachineFunctionPass that adds prefetch instructions to a function. I have code that adds a "prefetchnta <constant address>" instruction to x86 32-bit code. What I want to do is to add a "prefetchnta <constant address>" instruction to x86_64 code. Given that you don't actually

On 9/11/12 12:10 PM, Stephen Checkoway wrote: > On Sep 11, 2012, at 10:57 AM, John Criswell wrote: > >> I'm working on an X86 MachineFunctionPass that adds prefetch instructions to a function. I have code that adds a "prefetchnta <constant address>" instruction to x86 32-bit code. What I want to do is to add a "prefetchnta <constant address>"

-----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of John Criswell Sent: Tuesday, September 11, 2012 1:42 PM To: Steve Checkoway Cc: LLVMdev at cs.uiuc.edu Subject: Re: [LLVMdev] Need Help Understanding Operands in X86 MachineFunctionPass ... > >> The code for adding the 32-bit instruction is: >> >>

Trying again from the correct email address, sorry if you get this twice. On Sep 11, 2012, at 10:57 AM, John Criswell wrote: > I'm working on an X86 MachineFunctionPass that adds prefetch instructions to a function. I have code that adds a "prefetchnta <constant address>" instruction to x86 32-bit code. What I want to do is to add a "prefetchnta <constant

Hi, I'm still having problems implementing my custom inserter in the X86 backend. I found a solution to my last problem (http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-October/078296.html), by using a virtual register. The binary works when it's compiled in -O0, but not in -O1,-O2,... I really can't figure what I'm doing wrong... Any idea? Here is the code of my custom

Thank you for your help Tom you are totally right with the registers but the command you suggest also doesn't work. After some research I found the following thread on the mailing list: http://lists.llvm.org/pipermail/llvm-dev/2017-February/110086.html With your help and the information about the condition codes I was able to resolve the error:         BuildMI(BB, BB.end(), DL,

On 03/22/2018 09:29 AM, Julius Hiller via llvm-dev wrote: > Hello everyone, > > I'm working on a MachineFunctionPass that inserts a list of instructions into an Module so a later Pass can work on them. > To do so I load a dummy .ll file created from a main stub, create the needed function stubs (ModulePass), insert Blocks and create instructions using BuildMI. > I started with

Hi, I'm having trouble using virtual register in the X86 backend. I implemented a new intrinsic and I use a custom inserter. The goal of the intrinsic is to set the content of the stack to zero at the end of each function. Here is my code: MachineBasicBlock * X86TargetLowering::EmitBURNSTACKWithCustomInserter( MachineInstr *MI, MachineBasicBlock

Hi, I'm trying to emit a conditional move in the ARM backend for a custom intrinsic. Basically, I want to emit the following the following instruction sequence: cmp r0, r1 moveq r2, #1 To implement this, I first emit a compare instruction and then I'm trying to emit the conditional move, which is failing. BuildMI(&MBB, DL, TII->get(ARM::CMPrr))

For my target, I handle incoming memory arguments by creating a store to memory (in LowerCall, [1]), then creating a fixed object on the stack and loading from it (in LowerFormalArguments[2]). This approach was based on MSP430. I now have the problem that the resulting loads in my output assembly are done assuming that the call stack looks something like: ------ MemArg ------ MemArg ------

>> // Increment loop variable and jmp >> BuildMI(*MBB_erase, MBB_erase->end(), db, >> TII->get(X86::ADD64ri32),reg).addReg(reg).addImm(8); > > It looks like this instruction is defining virtual register "reg" the second time. Thx for your answer... Why would it define it again? I just want to use this register and add something to it... Cheers

Hello everyone, I'm working on a MachineFunctionPass that inserts a list of instructions into an Module so a later Pass can work on them. To do so I load a dummy .ll file created from a main stub, create the needed function stubs (ModulePass), insert Blocks and create instructions using BuildMI. I started with branch instructions:     const TargetMachine &TM = MF.getTarget();

Hi, Thx for your help... Here is the IR code: ; ModuleID = 'foo_bar.c' target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" @.str = private unnamed_addr constant [6 x i8] c"MAIN\0A\00", align 1 ; Function Attrs: nounwind uwtable define i32 @main(i32 %argc, i8** %argv) #0 { entry: %retval = alloca i32,

Cool, that worked. New patch attached... Cheers, Gary Evan Cheng wrote: > Just cast both values to const TargetRegisterClass*. > > Evan > > On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > > Evan Cheng wrote: > > > How about? > > > > > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > > > &PPC:G8RCRegClass; >

Sorry, this is the part in ARMLoadStoreOptimizer.cpp that creates a LDRD instruction. Ops.pop_back(); Ops.pop_back(); // Form the pair instruction. if (isLd) { MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, TII->get(NewOpc)) .addReg(EvenReg, RegState::Define)

Hi all, I’m trying to insert some add/sub and push/pop instructions in a MachineFunction pass for ARMv7-M. However, I encountered something weird. For an add, when I use BuildMI(….., TII->get(ARM::tADDi8), reg).addReg(reg).addReg(reg).addImm(imm). if reg is R0 - R7, everything is fine: I would get something like adds r1, 4 But if I use R8 - R12 as the reg in the BuildMI, I wouldn’t get

Hi Stephen, > I'm not entirely sure what is wrong here - I assume it has something to do > with my 'special' instruction LDri_ab. This instruction is a load with an > 'address writeback' - ld.ab r0, [r1, 5] is equivalent to ld r0, [r1]; add > r1, r1, 5. As it was very difficult to match such behaviour automatically, I > actually only generate them manually for

Evan Cheng wrote: > You need to insert new basic blocks and update CFG to accomplish this. > There is a hackish way to do this right now. Add a pseudo instruction > to represent this operation and mark it usesCustomDAGSchedInserter. > This means the intrinsic is mapped to a single (pseudo) node. But it > is then expanded into instructions that can span multiple basic >

Hi All. I'm writing storeRegToStackSlot and loadFromStackSlot function for my Target. This Target can store/load one byte (not all word) from FrameIndex. If I need to store 16 bit register I will must to split it to two instruction like this: BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) .addFrameIndex(FrameIndex).addImm(0) .addReg(SrcReg, 0, Z80::subreg_lo); BuildMI(MBB, MI, dl,

Dear All, Currently I am trying to inject custom x86-64 assembly into a functions entry basic block. More specifically, I am trying to build assembly in a machine function pass from scratch. While the dumped machine function instruction info displays that %gs will be used, when I perform objdump -d on my executable I am see that %gs is replaced by %ebp? Why is this happening? I know it probably